EEL4930/5934 - Reconfigurable Computing


Midterm 2 Sample Problems

Here are some sample problems to practice for midterm 2. Check back for updated versions and additional problems.

Here is an updated version, please ignore the previous version. Solutions will be posted soon.

Yet another version, which fixes some typos, and clarifies some questions.

Here are the solutions for the sample problems. Sorry for the 2nd grade handwriting. On problem 9, the priorities use maximum cycle length, not maximum path length as discussed in class. I will clarify this during lecture.

Midterm 2

Midterm 2 will be on Wednesday, October 31. The format will be similar to the first midterm, but there will be less multiple choice.


The final has been moved to Monday Dec. 3. It will be held during lecture.


Fundamental concepts at advanced undergraduate level (EEL4930) and introductory graduate level (EEL5934) in reconfigurable computing based upon advanced technologies in field-programmable logic devices. Topics include general concepts, device architectures, design tools, metrics and kernels, system architectures, and application case studies.

Course Information


Lecture Date Topic Slides/Reading Material
1 F, Aug 24 Course info, Intro to RC Slides
Compton, Hauck Survey
2 M, Aug 27 RC Markets Slides
Chapters 1-4 (by next week)
3 W, Aug 29 FPGA Architectures Chapters 1-4
4 F, Aug 31 VHDL Tutorial, FPGA architectures cont. Online tutorial
5 W, Sept. 5 VHDL Tutorial, cont. Online tutorial
6 F, Sept. 7 VHDL Tutorial, cont. Online tutorial
7 M, Sept. 10 Nallatech Tutorial Nallatech Tutorial Slides
8 W, Sept. 12 FPGA Architectures 2 FPGA/Routing tutorial
9 F, Sept. 14 FPGA Architectures 3 FPGA/Routing tutorial
10 M, Sept. 17 Placement and Routing
11 W, Sept. 19 Nallatech Discussions
12 F, Sept. 21 Nallatech
13 M, Sept. 24 NP/P, Branch+Bound, Heuristics
14 W, Sept. 26 Placement and Routing 2 Maze Router Demonstration
15 F, Sept. 28 Placement and Routing 3 Circuit Partitioning Slides
Pathfinder Slides
16 M, Oct. 1 Placement and Routing 4
17 W, Oct. 3 Midterm 1
18 F, Oct. 5 Systolic Arrays A Quantitative Analysis of the Speedup Factors of FPGAs over Processors
19 M, Oct. 8 Systolic Arrays, Cont. Slides (Check back for updates)
20 W, Oct. 10 Systolic Arrays, Cont. Slides (Check back for updates)
21 F, Oct. 12 Systolic Arrays, Cont. Slides (Check back for updates)
22 M, Oct. 15 High-Level Synthesis Intro Slides
23 W, Oct. 17 High-Level Synthesis: Front-End Slides
24 F, Oct. 19 High-Level Synthesis: Scheduling Slides
25 M, Oct. 22 High-Level Synthesis: Scheduling 2 Slides
26 W, Oct. 24 High-Level Synthesis: Scheduling 3 Slides Changes from previous version - Slide 89 was modified, several binding slides were added at the end of the section.
27 F, Oct. 26 High-Level Synthesis: Binding/Resource Sharing Slides Changed slides: 18, 49-51, 58, 61, 75, 81, 83, 93, 104, 106-114
28 M, Oct. 29 Midterm Review
29 W, Oct. 31 Midterm 2
30 M, Nov. 5 Buffering Techniques High-level Synthesis Slides 1.6 (only last few slides changed)
Buffer Slides
Smart Buffer paper
31 W, Nov. 7 Hardware/Software Partitioning Updated buffer slides (changes to smart buffer slides)
System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search
32 F, Nov. 9 Smart Buffers/Final Project Discussion
33 W, Nov. 14 Hw/Sw Partitioning Hw/Sw Slides
An Evaluation of Bipartitioning Techniques
34 F, Nov. 16 Warp Processing Warp Processing Slides
Warp Processors
Thread Warping
35 M, Nov. 19 RC Performance Prediction Slides
Performance Prediction Paper
RAT Paper
36 W, Nov. 21 Partial Reconfiguration Slides
Partial Reconfiguration Paper
37 M, Nov. 26 Performance Analysis Slides
Performance Analysis Paper
38 W, Nov. 28 Device Characterization/Tradeoff Analysis Slides
Density Advantage of RC Paper