The objectives of this course are to learn, understand, and extend existing design techniques for FPGAs and other reconfigurable devices. Specific goals include gaining experience with advanced pipelining strategies, techniques for creating scalable, high-frequency pipelines, experience with FPGA virtualization strategies and high-level synthesis tools, while also evaluating FPGA application studies in embedded and high-performance domains.
| Date | Topic | Slides/Reading Material |
|---|---|---|
| M, Jan 9 | Course info, Intro |
Slides Start reading my SystemVerilog tutorial. |
| W, Jan 11 | SystemVerilog: Combinational Logic (Basic constructs, 2x1 mux, 4-input priority encoder) |
Github repo for combinational logic 2x1 mux code 4-input priority encoder |
| F, Jan 13 | SystemVerilog: Combinational Logic (4-input priority encoder, parameterized priority encoder) | Parameterized priority encoder |
| W, Jan 18 | SystemVerilog: Combinational Logic (Adder, Multiplier, ALU) |
Adder code Multiplier code ALU code |
| F, Jan 20 |
SystemVerilog: Combinational Logic, Cont. (ALU, Misc.) SystemVerilog: Structural Architectures |
Github repo for structural architectures |
| M, Jan 23 |
SystemVerilog: Structural Architectures, Cont. SystemVerilog: Sequential Logic |
Github repo for sequential logic Blocking vs. Non-blocking assignments |
| W, Jan 25 |
SystemVerilog: Sequential Logic, Cont. |
Sequential logic example Schematic of architectures |
| F, Jan 27 |
SystemVerilog: Sequential Logic, Cont. SystemVerilog: Finite State Machines |
Github repo for FSMs FSM Design & Synthesis using SystemVerilog |
| M, Jan 30 |
SystemVerilog: Finite State Machines, Cont. SystemVerilog: Finite State Machines and Datapaths (FSMDs) |
Github repo for FSMs + Datapaths |
| W, Feb 1 | SystemVerilog: Finite State Machines and Datapaths (FSMDs), Cont. | |
| F, Feb 3 | SystemVerilog: FSMDs | |
| M, Feb 6 |
SystemVerilog: FSM+Ds Lab 1 |
|
| W, Feb 8 |
Basic Linters Lab servers SV testbenches: basic mux example |
Information on using lab servers Github repo for basic testbenches Lecture from 2022 |
| F, Feb 10 |
SV testbenches: basic examples, race conditions x2go demonstration |
Race condition examples Lecture from 2022 (Part 1, Skip to 8:50) Lecture from 2022 (Part 2) |
| M, Feb 13 | SV testbenches: reset race conditions, basic register testbench. | Lecture from 2022 |
| W, Feb 15 | SV testbenches: assertions, implication |
Github repo Doulos assertions tutorial Lecture from 2022 |
| F, Feb 17 | SV testbenches: assertions, implication, cont. | Lecture from 2022 |
| M, Feb 20 | SV testbenches: assertions, implication, cont. | Lecture from 2022 |
| W, Feb 22 |
SV testbenches: assertions, implication, cont. SV testbenches: coverage (cover properties) |
Coverage examples Lecture from 2022 |
| F, Feb 24 | Midterm Review | Lecture from 2022 |
| M, Feb 27 | Hw/Sw Co-Simulation, Intel ASE |
Intel PAC Overview Intel PAC RTL Training Examples |
| W, Mar 1 | SV testbenches: cover properties, coverpoints, covergroups | |
| F, Mar 3 | Midterm | |
| M, Mar 6 | SV testbenches: coverpoints/covergroups (cont.), constrained-random verification (CRV) | CRV examples |
| W, Mar 8 | SV testbenches: constrained-random verification (CRV), cont. | |
| F, Mar 10 | SV testbenches: constrained-random verification (CRV), cont. | |
| M, Mar 20 | SV testbenches: constrained-random verification (CRV), cont. |
Finish reading bit_diff_tb example.
Video 1 Video 2 (forgot to share my screen) Video 3 |
| W, Mar 22 | SV testbenches: object-oriented testbenches |
Object-oriented alternative to bit_diff_tb See Video 3 from previous lecture (jump to 44 min) |
| F, March 24 |
UVM overview Timing analysis background |
UVM tutorial UVM Hello World EDA Playground UVM Examples Github repo for timing optimization (includes slides) Lecture from 2022 |
| M, March 27 | Timing Optimization: background, common strategies |
Background video Github repo for timing optimization (includes slides) |
| W, March 29 | Timing Optimization: common strategies | Timing optimization strategies video |
| F, March 31 | Timing Optimization: Quartus timing analyzer overview, add tree example |
Timing analyzer overview Add tree example |
| M, April 3 | Timing Optimization: timer examples |
Example 1 Example 2 |
| W, April 5 | Timing Optimization: register duplication |
Register duplication example |
| F, April 7 |
Timing Optimization: reset reduction, reset tree, multi-cycle paths, counter, FSMD tips Lab 4 |
Reset reduction example Reset tree example Multi-cycle paths Counter FSM(D) tips slides |
| M, April 10 | Heterogeneous Parallel Programming: C++ crash course |
C++ Slides |
| W, April 12 | Heterogeneous Parallel Programming: C++ (cont.), OpenCL Overview |
OpenCL Slides SYCL Vector Add |
| F, April 14 | Heterogeneous Parallel Programming: OpenCL Overview (Cont.) | |
| M, April 17 | SYCL: Introduction, Vector Add Example |
SYCL Vector Add |
| W, April 19 | SYCL: Multiple kernels, parameter passing, SAXPY example, multi-kernel/device SAXPY |
SYCL SAXPY Multi-kernel/device SAXPY |
| F, April 21 | SYCL: FPGA code, accumulation, synchronization, local memory |
FPGA Examples Accumulation Examples Accumulation Slides (incomplete) |