Lab 1 - FSM + Datapath in SystemVerilog (Due Feb. 15)

• Lab Instructions
• Provided skeleton code
• Provided testbench

Lab 2 - Hw/Sw Co-simualtion with Intel ASE (Due March 8)

• Lab Instructions
• Provided code

Lab 3 - SystemVerilog Testbenches (Due March 31)

• Lab Instructions
• All lab files

Lab 4 - Timing Optimization (Due April 21)

• Lab Instructions
• Provided Files

Lab 5 - SYCL Tutorial (Due April 28)

• Lab Instructions
• Provided Files