Midterm 1 will be on Friday, Feb 17. Midterm 2 will be on Friday, March 24. Midterm 3 will be Wed, April 26. There is no final.
Late penalties for labs are 20% for the first day and 10% for each additional day.
Advanced modular logic, design languages, finite state machines and binary logic.
This course will review basic concepts in digital logic (muxes, decoders,
encoders, etc.) and will build upon these concepts to form complex digital
circuits consisting of finite state machines, controllers, and datapaths. The
course will be lab intensive and will provide realistic case studies to apply
concepts learned during lecture. All concepts discussed in lecture will be
implemented in VHDL.
| Date | Topic | Slides/Reading Material |
|---|---|---|
| M, January 9 | Course Intro |
Slides |
| W, January 11 | VHDL Intro (guidelines, entity and architecture, basic mux implementation) |
VHDL Tutorial 2x1 Mux Example VHDL Tutorial: Combinational Logic |
| F, January 13 | VHDL Intro (if vs. case, priority encoder, structural architectures) |
VHDL 4-input Priority Encoder VHDL 4:1 Mux Structural Architecture VHDL Tutorial: Structural Architectures |
| M, January 16 | Holiday | |
| W, January 18 | Lab 1 | |
| F, January 20 | Arithmetic Operations, Signals Vs. Variables | VHDL Tutorial: Adder example with different packages |
| M, January 23 | ALU, Generics, Avoiding Latches | VHDL Tutorial: ALU Example |
| W, January 25 | Lab 2, Testbenches | See testbench examples on VHDL tutorial. |
| F, January 27 | Carry-Lookahead Adders |
Slides See Section 5.4 in book |
| M, January 30 | Lab 3, For Generate | |
| W, February 1 |
Lab 3, Cont. Misc VHDL (configurations, initialization of signals, advanced testbenches, generics, components, vho/vhd, package reference, Modelsim tricks) |
|
| F, February 3 | Sequential Logic | VHDL Tutorial: Sequential Logic |
| M, February 6 |
Sequential Logic, Cont. Lab 4 |
Lecture from 2022 |
| W, February 8 |
Finite State Machines (FSMs) Lab 4, Cont. |
VHDL Tutorial: FSMs Lecture from 2022 |
| F, February 10 | Midterm 1 Review | Lecture from 2022 |
| M, February 13 | Sequential Logic Testbenches, Counters, Integers |
VHDL Tutorial: Counters Lecture from 2022 |
| W, Feb 15 | FSMD |
VHDL Tutorial: FSMDs
Fibonacci Calculator FSMD (1-process model) Fibonacci code and datapath Lecture from 2022 |
| F, Feb 17 | Midterm 1 | |
| M, Feb 20 | FSM+D, Lab 5 | Lecture from 2022 |
| W, Feb 22 |
FSM+D, Cont. |
Lecture from 2022 |
| F, Feb 24 | VGA, Lab 6 |
VGA Interface Slides
Lab 6 Slides |
| M, Feb 27 | Lab 6, Cont. | |
| W, Mar 1 |
Lab 6, Cont. VHDL Arrays Delay Entity |
Delay example |
| F, Mar 3 |
VHDL Arrays, Cont. Delay Entity, Cont. |
|
| M, Mar 6 |
Midterm 1 Solution Delay Entity, Cont. FPGA Architectures |
FPGA Architecture Slides
Max 10 Overview |
| W, Mar 8 | FPGA Architectures, Cont. | |
| F, Mar 10 | FPGA Architectures, Cont. | |
| M, Mar 20 | Midterm 2 Review | Lecture from 2022 |
| W, Mar 22 | MIPS: Overview, register file, ALU, datapath, memory |
Example register file (not the one for the MIPS) Lecture from 2022 |
| F, Mar 24 | Midterm 2 | |
| M, Mar 27 | MIPS: Register file, memory, instruction fetch, instruction decode | |
| W, Mar 29 | MIPS: instruction fetch, instruction decode, r-type instructions | |
| F, Mar 31 | MIPS: r-type instructions, i-type instructions | |
| M, April 3 | MIPS: i-type instructions, load/store instructions, jump instructions | |
| W, April 5 | MIPS: branch instructions | |
| F, April 7 | MIPS: MIF files, assembly code | |
| M, April 10 | Metastability, Clock-Domain Crossing |
Papers Basics of setup and hold time |
| W, April 12 |
Metastability, Clock-Domain Crossing Buses, tristates RAM |
Bus/Tristate Code RAM |
| F, April 14 | Pareto-optimality, Design-space exploration | |
| M, April 17 |
Pareto-optimality, Design-space exploration, Cont. Pipelining, loop unrolling |
|
| W, April 19 |
ASIC vs FPGA design flows and optimizations Research: Hardware security, IP redaction |
|
| F, April 21 |
Research: ATPG for redacted IP Midterm 3 review |
|
| M, April 24 | Research: elastic IP, approximate computing, symbolic regression, genetic programming |
Elastic IP slides Elastic IP video PANDORA slides FPGA Acceleration of Genetic Programming |