Midterm 1 will be on Friday, Feb 11. Midterm 2 will be on Friday, March 18. Midterm 3 will be Wed, April 20. There is no final.
Late penalties for labs are 20% for the first day and 10% for each additional day.
Advanced modular logic, design languages, finite state machines and binary logic.
This course will review basic concepts in digital logic (muxes, decoders,
encoders, etc.) and will build upon these concepts to form complex digital
circuits consisting of finite state machines, controllers, and datapaths. The
course will be lab intensive and will provide realistic case studies to apply
concepts learned during lecture. All concepts discussed in lecture will be
implemented in VHDL.
| Date | Topic | Slides/Reading Material |
|---|---|---|
| W, January 5 | Course Intro |
Slides |
| F, January 7 | VHDL Intro (guidelines, entity and architecture, basic mux implementation) | VHDL Tutorial (See 2x1 mux example) |
| M, January 10 | VHDL Intro (if vs. case, priority encoder, structural architectures) |
Tutorial (read combinational logic and structural description sections)
4x1 mux See Ch. 6 for priority encoder example. |
| W, January 12 | Lab 1 | |
| F, January 14 | Arithmetic Operations |
Add w/ carry examples in different packages: numeric_std std_logic_arith with std_logic_unsigned std_logic_arith Common Problems: Signal/variable comparison |
| M, January 17 | Holiday | |
| W, January 19 | ALU, Generics, Avoiding Latches | See ALU example on my VHDL tutorial. |
| F, January 21 | Lab 2, Testbenches | |
| M, January 24 | Carry-Lookahead Adders |
Slides Read Section 5.4 |
| W, January 26 | Lab 3, For Generate | |
| F, January 28 |
Lab 3, Cont. Misc VHDL (configurations, initialization of signals, advanced testbenches, generics, components, vho/vhd, package reference, Modelsim tricks) |
|
| M, January 31 | Sequential Logic | |
| W, February 2 |
Sequential Logic, Cont. Lab 4 |
|
| F, February 4 | Midterm 1 Review | |
| M, February 7 |
Finite State Machines (FSMs) |
|
| W, February 9 | Sequential Logic Testbenches, Counters, Integers | See tutorial. Counter link. |
| F, February 11 | Midterm 1 | |
| M, Feb 14 | FSMD |
See Controllers+Datapath section of VHDL tutorial. Fibonacci Calculator FSMD (1-process model) Fibonacci code and datapath |
| W, Feb 16 | FSM+D, Lab 5 | |
| F, Feb 18 |
FSM+D, Cont Midterm 1 Solution |
|
| M, Feb 21 | VGA, Lab 6 |
VGA Interface Slides
Lab 6 Slides |
| W, Feb 23 |
Lab 6, Cont. Delay Entity |
Delay example 1
Delay example 2 |
| F, Feb 25 |
Lab 6, Cont. Delay Entity, Cont. |
|
| M, Feb 28 | FPGA Architectures |
FPGA Architecture Slides
Max 10 Overview |
| W, Mar 2 | FPGA Architectures, Cont. | |
| F, Mar 4 | FPGA Architectures, Cont. | |
| M, Mar 14 | Midterm 2 Review | |
| W, Mar 16 | MIPS: Overview, register file, ALU, datapath, memory | Example register file (not the one for the MIPS) |
| F, Mar 18 | Midterm 2 | |
| M, Mar 21 | MIPS: Register file, memory, instruction fetch, instruction decode | |
| W, Mar 23 | MIPS: instruction fetch, instruction decode, r-type instructions | |
| F, Mar 25 | MIPS: r-type instructions, i-type instructions | |
| M, Mar 28 | MIPS: jump/branch instructions | |
| W, Mar 30 |
MIPS: jump/branch instructions, cont. Midterm 2 Solution | |
| F, April 1 | MIPS: MIF examples, simulation tips | |
| M, April 4 | Metastability, Clock-Domain Crossing |
Papers Basics of setup and hold time |
| W, April 6 |
Metastability, Clock-Domain Crossing Buses, Tri-states |
Bus/Tristate Code |
| F, April 8 |
VHDL arrays Pareto-optimality, Design-space exploration |
|
| M, April 11 | Pareto-optimality, design-space exploration, pipelining | |
| W, April 13 | Research topics: elastic IP, approximate computing |
Elastic IP slides Elastic IP video PANDORA slides |
| F, April 15 | Midterm Review | |
| M, April 18 | Research topics | |
| W, April 20 | Midterm 2 |