Lab workarounds

If you run into unexplainable errors, make sure your Quartus and/or Modelsim projects are stored in a path without any spaces. It seems to have fixed the problems for some people.

If you are doing a timing simulation, make sure to remove the original vhd file from the Modelsim project. If you don't, two files will define the same entity, which will likely cause problems.

If you can't find the USB-Blaster device in Windows, try the following suggestions:

• Within device manager, if you double click on the Altera USB-Blaster, and go to the Driver tab, press on Update Driver, then press Browse my computer for driver software -> browse. This is where you find the file. In my case, and for most people, it should be under: Local Disk (C:) -> intelFPGA_lite -> 17.1 -> quartus -> drivers -> usb-blaster. Select that folder and press ok. Then press next in the update driver window and it will load it with functional drivers.
• 1. go to device manager
  2. right click on usb-blaster and select update
  3. browse my computer for drivers
  4. "let me pick from a list of available drivers on my computer"
  5. scroll down and click on "JTAG Cable"
  6. Altera USB-Blaster II (JTAG interface)
  7. click next
  8. click yes
  
• 1 - Go to windows 10 settings and search for "advanced startup options"
  2 - Under Advanced startup, hit "Restart now"
  3 - After a moment, you'll get a "choose an option" screen - choose "Troubleshoot", then "Advanced options", then "Startup Settings"
  4 - You'll get a screen telling you what you will be able to change and a single "Restart" button - press it.
  5 - If your boot drive is BitLocker encrypted, you'll need to enter the recovery key (press return, enter the key in the text box then hit return again - it took me three goes to realize I had to hit return before I could enter they key !)
  6 - You'll be given a menu of options, number 7 disables driver signature enforcement
  7 - When the PC restarts, use Device manager to update the drivers - this time you'll get a warning about the signature, but they install fine.
  8 - When you've finished, restart normally to re-enable signature enforcement
  

If Quartus isn't generating an SDO file after synthesis, try the following:

• Make sure you aren't using the MAX10 FPGA.
• Assignments (in the top bar) -> Settings (2nd option) -> Simulation (Under the EDA tool settings dropdown) -> More EDA Netlist Writer Settings (Button) -> And then turn the Generate functional simulation netlist to off to generate the SDO.

Lab 0: (Week 2: Jan 10-14)

1. Obtain and test board in lab. If you have questions about the board, you can read the manual here.
2. Install Quartus Prime 17.1 Lite Edition (free) . Before downloading, make sure the ModelSim option is selected. You can unselect device support for everything except the MAX 10, MAX II, and MAX V FPGAs if you need to save disk space.
3. Read over the following tutorials (ignore references to lab assignment tasks. You will be using these tools as part of the next lab)
   • Oscillosope Tutorial
   • Signal Tap Tutorial (ignore line ment ioning "Incremental Build")
   • Digilent Analog Discovery Getting Started
4. Review Quartus Tutorials 1 and 3 (Appendices in textbook)
5. Start reading the ModelSim tutorial. You do not need to finish the entire tutorial, but you will be using this tool all semester, so make sure you understand the basics. You can install a free version of Modelsim from the earlier Quartus link.

Lab 1: Introduction to EEL 4712 Digital Design Lab (Week 3: Jan 18-Jan 24)

• Lab Instructions
• Provided Code
• Pin assignment instructions
• Pin assignment tutorial
  
  
• Solution if Quartus is not producing sdo file (appears to apply to Quartus 19+).
  
  
• Checklist

Lab 2: Generic-Width Behavioral ALU (Week 4: Jan 25-Jan 31)

• Lab Instructions
• Small sample testbench for alu_ns
• Top level entity

You will find these incredibly useful:

• VHDL Package Reference
• VHDL Math Tricks (Comparison of std_logic_arith and numeric_std)

• Lab 2 Checklist

Lab 3: Ripple-Carry and Carry-Lookahead Adders (Week 5: Feb1-Feb7)

• Lab Instructions
• Adder entity skeleton code
• Provided testbench
• Top-level entity

• Top-level for timing simulation
• Testench for timing simulation

• Lab 3 Checklist

Lab 4: Finite State Machines (Week 7: Feb15-Feb21)

• Lab Instructions
• All provided code

• Lab 4 Checklist

Lab 5: GCD Calculator (Week 8: Feb 22-Feb 28)

• Lab Instructions
• All provided code
• For additional extra credit, please test the vJTAG interface that enables communication between your laptop and board. First, download extra_credit.zip. Read the instructions in GUI_Instructions.doc. Add your lab5 gcd code to the specified project. As part of the pre-lab submission, create a separate report that specifies the operating system version you are using, and any problems you encountered. Future labs will use a polished version of this interface, so I'm looking for any suggestions you might have.

• Lab 5 Checklist

Lab 6: VGA Interfacing (Week 9-10: March1-March21)

• Lab Instructions
• MIF file instructions
• All provided code
• Tutorial on how to use the provided testbench
• Excellent video explaining how monitors work

• Lab 6 Checklist

Workarounds:

• If you are getting the following error:
  
  "Error (16031): Current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM."
  
  you can fix it with the following:
  
  Assignments -> Device -> Device and Pin Options -> Configuration -> Configuration Mode: Single uncompressed image with Memory Initialization

Final Project: MIPS-like Microprocessor (3 weeks, starts on Tuesday, March 29)

• Instructions (SUBJECT TO CHANGE)
• All provided material