Midterm 1 will be on Friday, Feb 15 in class. Midterm 2 will be on Friday, March 22. Midterm 3 will be Wed, April 24. There is no final.
Advanced modular logic, design languages, finite state machines and binary logic.
This course will review basic concepts in digital logic (muxes, decoders,
encoders, etc.) and will build upon these concepts to form complex digital
circuits consisting of finite state machines, controllers, and datapaths. The
course will be lab intensive and will provide realistic case studies to apply
concepts learned during lecture. All concepts discussed in lecture will be
implemented in VHDL.
| Date | Topic | Slides/Reading Material |
|---|---|---|
| M, January 7 | Course Intro | Slides |
| W, January 9 | VHDL Intro (guidelines, entity and architecture, basic mux implementation) | Tutorial (See 2x1 mux example) |
| F, January 11 | VHDL Intro (if vs. case, priority encoder, structural architectures) |
Tutorial (read combinational logic and structural description sections)
4x1 mux See Ch. 6 for priority encoder example. |
| M, January 14 | Arithmetic Operations |
Add w/ carry examples in different packages: numeric_std std_logic_arith with std_logic_unsigned std_logic_arith Common Problems: Signal/variable comparison |
| W, January 16 | Lab 1 | |
| F, January 18 | Class Cancelled | |
| M, January 21 | Holiday | |
| W, January 23 | Lab 2, Generics, Avoiding Latches, Testbenches | |
| F, January 25 | Testbenches, Carry-Lookahead Adders |
Carrry-Lookahead Slides Read Section 5.4 |
| M, January 28 | Lab 3, For-generate | |
| W, January 30 | Misc. VHDL (configurations, initialization of signals, advanced testbenches, generics, components, vho/vhd, package reference, Modelsim tricks) | |
| F, February 1 | Sequential Logic (see tutorial examples) | |
| M, Feb 4 | Sequential Logic, Cont. Finite State Machines |
See tutorial. Direct link. |
| W, Feb 6 | Finite State Machines, Cont. Lab 4 |
|
| F, Feb 8 | Midterm 1 Review | |
| M, Feb 11 | Lab 4 Cont., Counters, Integers. | See tutorial. Counter link. |
| W, Feb 13 | FSMD |
See Controllers+Datapath section of VHDL tutorial. Fibonacci Calculator FSMD (1-process model) Fibonacci code and datapath |
| F, Feb 15 | Midterm 1 | |
| M, Feb 18 | FSMD, FSM+D, Lab 5 |
See Controllers+Datapath section of VHDL tutorial. Fibonacci Calculator FSMD (1-process model) Fibonacci code and datapath |
| W, Feb 20 | FSMD, FSM+D, Lab 5, Cont. | |
| F, Feb 22 | Midterm 1 Solution, Lab 5 | |
| M, Feb 25 |
Lab 5 Extra Credit,
FSMD done protocol,
2-process FSMD |
2-process FSMD code |
| W, Feb 27 |
2-process FSMD, cont. Lab 6 |
|
| F, Mar 1 | Lab 6, cont. | |
| M, Mar 11 | FPGA Architectures |
FPGA Architecture Slides
Max 10 Overview |
| W, Mar 13 | FPGA Architectures, Cont. | |
| F, Mar 15 | FPGA Architectures, Cont. Midterm 2 Review |
|
| M, Mar 18 | MIPS (Arrays, RAM, Register File) |
Sample RAM Code Sample Register File Code |
| W, Mar 20 | MIPS (Register File, ALU, Datapath) | |
| F, Mar 22 | Midterm 2 | |
| M, Mar 25 | MIPS (Memory, I/O Ports, Instruction Fetch, Instruction Decode, Register Fetch) | |
| W, Mar 27 | MIPS (R-type Instructions) | |
| F, Mar 27 | Midterm 2 Solution, MIPS (R-type Instructions) | |
| M, April 1 | MIPS (I-type Instructions, Jump Instructions) | |
| W, April 3 | MIPS (Branch Instructions, MIF Files, Assembly Code) | |
| F, April 5 | Metastability, Clock-Domain Crossing |
Papers CDC overview |
| M, April 8 |
Metastability, Cont. Buses, Tristates |
Bus/Tristate Code |
| W, April 10 |
Buses, Tristates, Cont. Research Overview |
Application case study example: A performance and energy comparison of FPGAs, GPUs, and multicores for sliding-window applications Intel Xeon+FPGA study: Scalable Window Generation for the Intel Broadwell+Arria 10 and High-Bandwidth FPGA Systems FPGA Virtualization study: Virtualization Slides Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing |
| F, April 12 | Approximate Computing Research Overview | See email. |
| M, April 15 |
Pareto Optimality Design-space exploration |
|
| W, April 17 |
Pareto Optimality Design-space exploration |