EEL4712 Digital Design (Spring 2014)


Previous Midterms

Midterm 1 will be on Friday, Feb 14 in class. Midterm 2 will be on Friday, March 21. Midterm 3 will be Wed, April 23. There is no final.

Catalog Description

Advanced modular logic, design languages, finite state machines and binary logic.


This course will review basic concepts in digital logic (muxes, decoders, encoders, etc.) and will build upon these concepts to form complex digital circuits consisting of finite state machines, controllers, and datapaths. The course will be lab intensive and will provide realistic case studies to apply concepts learned during lecture. All concepts discussed in lecture will be implemented in VHDL.

Course Information


Date Topic Slides/Reading Material
M, January 6 Course Intro Slides
W, January 8 VHDL Intro (guidelines, entity and architecture, basic mux implementation) Tutorial
F, January 10 VHDL Intro (if vs. case, priority encoder, structural architectures) Tutorial (read combinational logic and structural description sections)
4x1 mux used in class
See Ch. 6 for priority encoder example.
M, January 13 Structural Architectures, Cont. Lab 1
W, January 15 Arithmetic Operations Add w/ carry examples in different packages:
std_logic_arith with std_logic_unsigned

Common Problems:
Signal/variable comparison
F, January 17 Arithmetic Operations Cont., Generics, Testbenches Read the combinational logic section of my tutorial, including the testbenches.
M, January 20 Holiday
W, January 22 Lab 2
F, January 24 Carry-Lookahead Adders Read Section 5.4
M, January 27 For Loops, Constants, Initialization of Signals, Literals, Misc. Functions/Operators
W, January 29 Lab 3, Configurations, For-generate
F, January 31 Class Cancelled
M, February 3 Sequential Logic See tutorial
W, February 5 Sequential Logic, Cont.
F, February 7 Midterm 1 Review
M, February 10 Finite State Machines See Tutorial
W, February 12 Lab 4
F, February 14 Midterm 1
M, February 17 FSMD See Controllers+Datapath section of VHDL tutorial.
Fibonacci Calculator FSMD (1-process model)
Fibonacci code and datapath
Exact code from class
W, February 19 FSM+D, Lab 5
F, February 21 Midterm 1 discussion, Datapath design
M, February 24 Arrays, If generate See delay entity from tutorial.
W, February 26 Arrays, If generate, Cont., Lab 6
F, February 28 Lab 6
M, March 10 FPGA Architectures FPGA Architecture Slides
Cyclone II Datasheet
Cyclone II Figures
Cyclone II Family Overview
W, March 12 FPGA Architectures, Cont.
F, March 14 FPGA Architectures, Cont.
M, March 17 Class Cancelled
W, March 19 Midterm 2 Review
F, March 21 Midterm 2
M, March 24 Small 8 Intro, Buses, Tristates
Bus/Tristate Code
W, March 26 Small 8 Intro, Buses, Tristates
F, March 28 Small 8 ALU, Buses
M, March 31 Small8 Opcode Fetch
W, April 2 Small8 Instruction Set
F, April 4 Small8 Instruction Set
M, April 7 Small8 Sample Programs
W, April 9 2-process FSMD, RAM, arrays 2-process FSMD code
Altera Guidelines for Memories (pg.12-35)
Xilinx Guidelines for Memories (pg.144-195)
F, April 11 Metastability, Clock-Domain Crossing Related papers
M, April 14 Metastability, Clock-Domain Crossing, Cont.
W, April 16 Design-space exploration, Pareto Optimality
F, April 18 Design-space exploration, Pareto Optimality, Cont.
M, April 21 Midterm Review
W, April 23 Midterm 3

VHDL Resources