library ieee; use ieee.std_logic_1164.all; entity mux_4x1 is port( in1, in2, in3, in4 : in std_logic; sel : in std_logic_vector(1 downto 0); output : out std_logic); end mux_4x1; architecture STR of mux_4x1 is signal mux1_output : std_logic; signal mux2_output : std_logic; begin U_MUX1 : entity work.mux_2x1 port map ( in1 => in1, in2 => in2, sel => sel(0), output => mux1_output ); U_MUX2 : entity work.mux_2x1 port map ( in1 => in3, in2 => in4, sel => sel(0), output => mux2_output ); U_MUX3 : entity work.mux_2x1 port map ( in1 => mux1_output, in2 => mux2_output, sel => sel(1), output => output ); end STR;