Fundamental concepts at advanced undergraduate level (EEL4720) and introductory graduate level (EEL5721) in reconfigurable computing based upon advanced technologies in field-programmable logic devices. Topics include general concepts, device architectures, design tools, metrics and kernels, system architectures, and application case studies.
| Date | Topic | Slides/Reading Material |
|---|---|---|
| M, Aug 24 | Course info, Intro to RC |
Slides Overview Paper: Compton, Hauck Survey Motivating FPGA Example: Scalable Window Generation for the Intel Broadwell+Arria 10 and High-Bandwidth FPGA Systems Tutorial: Start reading "My VHDL Tutorial" under VHDL Resources. |
| F, Aug 26 | VHDL: Introduction, Combinational Logic (2:1 Mux) |
Github tutorial for combinational logic
|
| M, Aug 29 | VHDL: Combinational Logic (adder) | |
| W, Aug 31 |
VHDL: Combinational Logic (ALU, latches) VHDL: Sequential Logic |
Github tutorial for sequential logic |
| F, Sep 2 |
VHDL: Sequential Logic, Cont. VHDL: Structural Architectures |
Github tutorial for structural architectures |
| W, Sep 7 |
VHDL: FSMs and FSMDs |
Github tutorial for FSMs
Github tutorial for FSMDs |
| F, Sep 9 | VHDL: FSMDs and FSM+Ds |
Github tutorial for FSMDs and FSM+Ds Example used in class |
| M, Sep 12 | VHDL: FSM+Ds, Testbenches | |
| W, Sep 14 | Device Tradeoffs |
Device tradeoff slides Extra video |
F, Sep 16 | Device Tradeoffs, Cont. FPGA Architectures |
Architecture Slides | M, Sep 19 | FPGA Architectures, Cont. | W, Sep 21 | Lab 2 | F, Sep 23 | Lab 2, FPGA Architectures, Cont. |
| M, Sep 26 | Optimization Problems | Slides |
| W, Sep 28 |
(Cancelled due to hurricane) Optimization Problems, Cont. |
Lecture from previous semester (skip the lab part in the beginning) |
| F, Sep 30 |
(Cancelled due to hurricane) Optimization Problems, Cont. RT Synthesis, Placement, and Routing |
Slides
Papers: Placement/Routing, Pathfinder, Versatile Place+Route (VPR) Lecture from previous semester Lecture 2 from previous semester (watch up to 34:00) |
| M, Oct 3 | Pipelining, Parallelism, Systolic Arrays | Pipelining Slides |
| W, Oct 5 |
Pipelining, Parallelism, Systolic Arrays, Cont. Midterm 1 Review |
Midterm 1 review from previous semester |
| F, Oct 7 | No class (homecoming) | |
| M, Oct 10 | Lab 3 | |
| W, Oct 12 | Midterm 1 | |
| F, Oct 14 |
Lab 3, Cont. Pipelining, Cont. |
|
| M, Oct 17 |
Midterm 1 Solution VHDL: for-generate |
For-generate example |
| W, Oct 19 | Misc VHDL |
Behavioral delay example
Structural delay example |
| F, Oct 21 |
Misc VHDL Lab 4 |
|
| M, Oct 24 | High-level Synthesis |
High-level Synthesis Slides |
| W, Oct 26 | High-level Synthesis, Cont. | |
| F, Oct 28 | High-level Synthesis, Cont. | |
| M, Oct 31 | High-level Synthesis, Cont. | |
| W, Nov 2 | Metastability, Clock-Domain Crossing |
Papers Basics of setup and hold time |
| W, Nov 4 |
Metastability, Clock-Domain Crossing, Cont. Lab 5 |
|
| M, Nov 7 | High-level Synthesis (Binding) | Lecture (Watch from 20:00 to end) |
| W, Nov 9 | Buffering |
Buffering Slides
Paper 1 Paper 2 Sliding-Window Paper Sliding-Window Paper on Broadwell+Arria10 |
| F, Nov 11 | Holiday | |
| M, Nov 14 |
Buffering, Cont. Final Project Overview |
|
| W, Nov 16 | Final Project (Pipeline, user_app) | |
| F, Nov 18 | Final Project (Signal/kernel buffers) | |
| M, Nov 21 | Final Project (dram_rd) | |
| M, Nov 28 |
Final Project (dram_wr) Misc Reset Tips 2-process FSMD |
2-process FSMD code Reset article 1 Tradeoffs between synchronous and asynchronous resets |
| W, Nov 30 | Midterm 2 Review | |
| F, Dec 2 | eFPGAs | Slides |
| M, Dec 5 | SYCL, DPC++ | Slides and code |
| W, Dec 7 | Midterm 2 |