EEL4720/5721 - Reconfigurable Computing (Fall 2016)


  • Midterm 1 has been changed to Monday October 10. EDGE students can take the test from October 10-12.
  • The late penalty for all assignments is 10% per day. Anything more than 5 minutes late is one day late.


    Fundamental concepts at advanced undergraduate level (EEL4720) and introductory graduate level (EEL5721) in reconfigurable computing based upon advanced technologies in field-programmable logic devices. Topics include general concepts, device architectures, design tools, metrics and kernels, system architectures, and application case studies.

    Course Information


    Date Topic Slides/Reading Material
    M, Aug 22 Course info, Intro to RC Slides
    Paper: Compton, Hauck Survey
    Tutorials: Start reading "My Tutorial" under VHDL Resources.
    W, Aug 24 VHDL Tutorial (Combinational Logic) See combinational logic section of "My Tutorial" under VHDL Resources.
    F, Aug 26 VHDL Tutorial (Combinational Logic, Cont.) See my tutorial.
    M, Aug 29 VHDL Tutorial (Sequential Logic, Cont.) See my tutorial.
    W, Aug 31 VHDL Tutorial (Sequential Logic, Cont., Structural Architectures) See my tutorial.
    F, Sep 2 Class cancelled See my tutorial.
    M, Sep 5 Holiday See my tutorial.
    W, Sep 7 VHDL Tutorial (Finite-State Machines, FSMD, FSM+D) See finite state machine section and controller+datapath section of tutorial.
    Additional FSMD example used in class
    F, Sep 9 VHDL Tutorial (FSMD, FSM+D, cont.)
    M, Sep 12 VHDL testbench overview
    Device Tradeoffs
    Measuring the Gap between FPGAs and ASICs
    W, Sep 14 Device Tradeoffs, Cont.
    FPGA Architectures
    Architecture Slides
    F, Sep 16 FPGA Architectures, Cont.
    M, Sep 19 FPGA Architectures, Cont.
    W, Sep 21 Lab 2
    F, Sep 23 Lab 2, Cont.
    FPGA Architectures, Cont.
    M, Sep 26 Optimization Problems Slides
    W, Sep 28 Optimization Problems, Cont.
    RT Synthesis, Placement, and Routing
    Papers: Placement/Routing, Pathfinder, Versatile Place+Route (VPR)
    F, Sep 30 RT Synthesis, Placement, and Routing, Cont.
    Lab 3
    M, Oct 3 Lab 3, Cont.
    Pipelining, Parallelism, Systolic Arrays
    Pipelining Slides
    W, Oct 5 Pipelining, Parallelism, Systolic Arrays, Cont.
    F, Oct 7 No class (hurricane)
    M, Oct 10 Midterm 1
    W, Oct 12 Pipelining, Parallelism, Systolic Arrays, Cont.
    Lab 4
    F, Oct 14 No Class (Homecoming)
    M, Oct 17 Pipelining, Parallelism, Systolic Arrays, Cont.
    Lab 4
    High-level Synthesis
    High-level Synthesis Slides
    W, Oct 19 High-level Synthesis, Cont.
    F, Oct 21 High-level Synthesis, Cont.
    M, Oct 24 High-level Synthesis, Cont.
    W, Oct 26 High-level Synthesis, Cont.
    F, Oct 28 High-level Synthesis, Cont.
    M, Oct 31 Metastability, Clock-Domain Crossing Papers
    W, Nov. 2 Metastability, Clock-Domain Crossing, Cont.
    Lab 5
    Basics of setup and hold time
    F, Nov 4 Buffering Buffering Slides
    Paper 1
    Paper 2
    Sliding-Window Paper
    M, Nov 7 Buffering, Cont.
    W, Nov 9 Final Project (DMA Interface for DRAM)
    M, Nov 14 Final Project (DMA Interface), Cont.
    Buffering, Cont.
    W, Nov 16 Final Project (Signal Buffer), Cont.
    2-process FSMD
    2-process FSMD code
    F, Nov 18 Final Project (User App), Cont. 2-process FSMD 2-process FSMD code
    M, Nov 21 Final Project (Padding, Arrays, Testbenches), Cont.
    M, Nov 28 Hw/Sw Partitioning Slides
    System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search
    An Evaluation of Bipartitioning Techniques
    W, Nov 30 Overlays, Virtualization, Fast Compilation Slides 1
    Slides 2
    Intermediate Fabrics
    Fast, Flexible High-Level Synthesis form OpenCL using Reconfiguration Contexts
    Adjustable-Cost Overlays for Runtime Compilation
    F, Dec 2 Midterm 2 Review
    M, Dec 5 Misc Topics Catapult Slides
    Amazon EC2 F1
    Amazon EC2 F1, Cont.
    Approximate Computing
    Space Computing

    VHDL Resources