EEL4720/5721 Labs (Fall 2016)

Useful References

Common Vivado Problems:

Lab 0 - Due Date: Sep 2 (Start Now!)


Lab Instructions
VHDL Files

Links:
Download Xilinx Vivado WebPACK (Make sure to get the WebPACK and not the full version)
Vivado tutorials:

Known Problems:

Lab 1 - Fibonacci Calculator (DUE SEP 19 11:59 PM)

Instructions

Make sure to read the controllers+datapaths section of my VHDL tutorial.

Lab 2 - ZedBoard Tutorial (DUE Sep 30, 11:59 PM)

Lab 3 - Fibonacci Calculator on ZedBoard (DUE OCT 12, 11:59PM)

Lab 4 - Simple Pipeline (DUE OCT 26, 11:59 PM), EXTENDED UNTIL MONDAY, OCT. 31, 11:59 PM

Lab 5 - Clock-domain crossing (DUE Nov 11, 11:59 PM)

Class Project - 1D Time-Domain Convolution (DUE December 9, 11:59PM) IMPORTANT: NO LATE SUBMISSIONS WILL BE ACCEPTED.