EEL4720/5721 - Reconfigurable Computing (Fall 2018)



Fundamental concepts at advanced undergraduate level (EEL4720) and introductory graduate level (EEL5721) in reconfigurable computing based upon advanced technologies in field-programmable logic devices. Topics include general concepts, device architectures, design tools, metrics and kernels, system architectures, and application case studies.

Course Information


Date Topic Slides/Reading Material
W, Aug 22 Course info, Intro to RC Slides
Overview Paper: Compton, Hauck Survey
Motivating FPGA Example: Scalable Window Generation for the Intel Broadwell+Arria 10 and High-Bandwidth FPGA Systems
Tutorial: Start reading "My VHDL Tutorial" under VHDL Resources.
F, Aug 24 VHDL Tutorial (Combinational Logic) See combinational logic section of "My VHDL Tutorial" under VHDL Resources.
M, Aug 27 VHDL Tutorial (Combinational Logic, Cont.) See my tutorial.
W, Aug 29 VHDL Tutorial (Sequential Logic) See my tutorial.
F, Aug 31 VHDL Tutorial (Sequential Logic, Cont., Structural Architectures) See my tutorial.
M, Sep 3 Holiday
W, Sep 5 VHDL Tutorial (Finite-State Machines, FSMD, FSM+D) See finite state machine section and controller+datapath section of tutorial.
Additional FSMD example used in class
F, Sep 7 VHDL Tutorial (FSMD, FSM+D, Testbenches)
M, Sep 10 VHDL Tutorial (FSM+D, Cont.)
Device Tradeoffs
Measuring the Gap between FPGAs and ASICs
W, Sep 12 Device Tradeoffs, Cont.
FPGA Architectures
Architecture Slides
F, Sep 14 FPGA Architectures, Cont.
M, Sep 17 FPGA Architectures, Cont.
W, Sep 19 Lab 2
F, Sep 21 Lab 2, Cont.
Misc. VHDL
M, Sep 24 Optimization Problems Slides
W, Sep 26 Optimization Problems, Cont.
RT Synthesis, Placement, and Routing
Papers: Placement/Routing, Pathfinder, Versatile Place+Route (VPR)
F, Sep 28 RT Synthesis, Placement, and Routing, Cont.
Pipelining, Parallelism, Systolic Arrays
Pipelining Slides
M, Oct 1 Pipelining, Cont.
W, Oct 3 Lab 3
F, Oct 5 Midterm 1 Review
M, Oct 8 Midterm 1
W, Oct 10 Pipelining, Cont.
F, Oct 12 VHDL: for-generate, if-generate, delay example
Lab 4
M, Oct 15 Lab 4, Cont.
High-Level Synthesis
High-level Synthesis Slides

VHDL Resources