Useful References

• Simulating in ModelSim/Questa from Vivado
• Adding the Zedboard to Vivado (see section on Install Digilent's Board Files)
• Unix/Linux Tutorial
• Another Unix/Linux Tutorial
• ZedBoard website
• ZedBoard Documentation
• Xilinx 7 Series FPGA Overview
• Xilinx 7 Series CLB Architecture
• Zynq Product Table
• AXI4 Specification

• Vivado hangs forever while generating HDL wrapper for block diagram.. Go to Tools->Settings->Text Editor->Syntax Checking and change Sigasi to Vivado.
• If you do not see the ZedBoard when creating a new project, there is a refresh button that updates the boards based on a Xilinx repository. This has worked in the past, but if the Zedboard still doesn't show up, you can follow the instructions here for installing Digilent's board files. You only need to copy the Zedboard folder, not all the folders as specified.
• The following error is caused by using a project path that has spaces. The only known workaround is to use a different path.
  
  ERROR: [Common 17-165] Too many positional options when parsing '-force', please type 'create_project -help' for usage info.
• If you add a VHDL file to an IP core and that file is already stored in the IP core's directory, do not check the box to copy the files into the repository. If you do check the box, Vivado will report an error that the file is already there and won't add the file to your project.
• If you are getting an error about an incorrect C++ version when installing Vivado, see the following:
  https://forums.xilinx.com/t5/Installation-and-Licensing/Vivado-Xilinx-SDK-Error-Incorrect-Visual-C-Version/td-p/442628

Lab 0 - Due Date: September 14

• Lab Instructions
• VHDL Files
• Download and install Vivado
  • 2024.1
• Vivado installation instructions
• Modelsim

Known Problems:

• If Vivado freezes during installation (e.g., while "verifying credentials"), try using the full installer instead of the web installer.