Midterm 1 will be on Friday, Feb 14 in class. Midterm 2 will be on Friday, March 20. Midterm 3 will be Wed, April 22. There is no final.
Advanced modular logic, design languages, finite state machines and binary logic.
This course will review basic concepts in digital logic (muxes, decoders,
encoders, etc.) and will build upon these concepts to form complex digital
circuits consisting of finite state machines, controllers, and datapaths. The
course will be lab intensive and will provide realistic case studies to apply
concepts learned during lecture. All concepts discussed in lecture will be
implemented in VHDL.
| Date | Topic | Slides/Reading Material |
|---|---|---|
| M, January 6 | Course Intro | Slides |
| W, January 8 | VHDL Intro (guidelines, entity and architecture, basic mux implementation) | Tutorial (See 2x1 mux example) |
| F, January 10 | VHDL Intro (if vs. case, priority encoder, structural architectures) |
Tutorial (read combinational logic and structural description sections)
4x1 mux See Ch. 6 for priority encoder example. |
| M, January 13 | Arithmetic Operations |
Add w/ carry examples in different packages: numeric_std std_logic_arith with std_logic_unsigned std_logic_arith Common Problems: Signal/variable comparison |
| W, January 15 | Lab 1 | |
| F, January 17 | Generics, ALU, Latches | See ALU example on my tutorial. |
| M, January 20 | Holiday | |
| W, January 22 | Lab 2, Guest Talk from L3Harris | L3Harris Slides |
| F, January 24 | Testbenches | |
| M, January 27 | Carry-Lookahead Adders, Lab 3 |
Carry-Lookahead Slides Read Section 5.4 |
| W, January 29 |
Lab 3, Cont. Misc. VHDL (configurations, initialization of signals, advanced testbenches, generics, components, vho/vhd, package reference, Modelsim tricks) |
|
| F, January 31 | Sequential Logic | |
| M, Feb 3 |
Sequential Logic, Cont. Finite State Machines |
|
| W, Feb 5 |
Finite State Machines Lab 4 |
|
| F, Feb 7 | Midterm 1 Review | |
| M, Feb 10 | Sequential Logic Testbenches, Counters, Integers | See tutorial. Counter link. |
| W, Feb 12 | FSMD |
See Controllers+Datapath section of VHDL tutorial. Fibonacci Calculator FSMD (1-process model) Fibonacci code and datapath |
| F, Feb 14 | Midterm 1 | |
| M, Feb 17 | FSM+D | |
| W, Feb 19 |
Lab 5, 2-process FSMD |
2-process FSMD code |
| F, Feb 21 | 2-process FSMD cont., Midterm 1 Solution | |
| M, Feb 24 | Lab 6 | |
| W, Feb 26 | Lab 6, Cont. | |
| F, Feb 28 | Static Timing Analysis | Slides |
| M, Mar 9 | FPGA Architectures |
FPGA Architecture Slides
Max 10 Overview |
| W, Mar 11 | FPGA Architectures, Cont. | |
| F, Mar 13 | FPGA Architectures, Cont. Midterm 2 Review |
|
| M, Mar 16 | Arrays, RAM, Register File |
See delay entity examples in tutorial.
Sample RAM Code Sample Register File Code |
| W, Mar 18 | MIPS (Register File, ALU, Datapath) | |
| F, Mar 20 | Midterm 2 | |
| M, Mar 23 | MIPS (Memory, I/O Ports, Instruction Fetch, Instruction Decode, Register Fetch) | |
| W, Mar 25 | MIPS (R-type Instructions) | |
| F, Mar 27 | MIPS (I-type, Jump, Branch, Load/Store) | |
| M, March 30 | MIPS (I-type, Jump, Branch, Load/Store), Cont. | |
| W, April 1 | MIPS MIF and Assembly Code | |
| F, April 3 | Buses, Tristates |
Bus/Tristate Code |
| M, April 6 | Metastability, Clock-Domain Crossing |
Papers CDC overview |
| W, April 8 | Metastability, Clock-Domain Crossing, Cont. | |
| F, April 10 | No lecture posted online. | |
| M, April 13 | Design-Space Exploration, Pareto-Optimality | |
| W, April 15 | Design-Space Exploration, Pareto-Optimality, Cont. | |
| F, April 17 | Midterm 3 Review | |
| M, April 19 | Timing closure, analysis, and optimization | |
| W, April 21 | Midterm 3 | |
| Bonus | Research Overview |
FPGA Virtualization study: Virtualization Slides Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing Approximate Computing PANDORA: a parallelizing approximation-discovery framework Application case study example: A performance and energy comparison of FPGAs, GPUs, and multicores for sliding-window applications Intel Xeon+FPGA study: Scalable Window Generation for the Intel Broadwell+Arria 10 and High-Bandwidth FPGA Systems |
