Midterm 1 will be on Friday, Feb 16 in class. Midterm 2 will be on Friday, March 23. Midterm 3 will be Wed, April 25. There is no final.
Advanced modular logic, design languages, finite state machines and binary logic.
This course will review basic concepts in digital logic (muxes, decoders,
encoders, etc.) and will build upon these concepts to form complex digital
circuits consisting of finite state machines, controllers, and datapaths. The
course will be lab intensive and will provide realistic case studies to apply
concepts learned during lecture. All concepts discussed in lecture will be
implemented in VHDL.
Date | Topic | Slides/Reading Material |
---|---|---|
M, January 8 | Course Intro |
Slides |
W, January 10 | VHDL Intro (guidelines, entity and architecture, basic mux implementation) | Tutorial (See 2x1 mux example) |
F, January 12 | VHDL Intro (if vs. case, priority encoder, structural architectures) |
Tutorial (read combinational logic and structural description sections)
4x1 mux See Ch. 6 for priority encoder example. |
W, January 17 | Lab 1 | |
F, January 19 | Arithmetic Operations |
Add w/ carry examples in different packages: numeric_std std_logic_arith with std_logic_unsigned std_logic_arith Common Problems: Signal/variable comparison |
M, January 22 | Lab 2, Generics, Avoiding Latches, Testbenches | |
W, January 24 | Lab 2, Cont. | |
F, January 26 | Carry-Lookahead Adders |
Slides Read Section 5.4 |
M, January 29 | Lab 3, For-generate | |
W, January 31 | Misc. VHDL (configurations, initialization of signals, advanced testbenches, generics, components, vho/vhd, package reference) | |
F, February 2 | Sequential Logic (see tutorial examples) | |
M, February 5 | Synthesis of Sequential Logic (see tutorial examples) | |
W, February 7 | Class Cancelled | |
F, February 9 | Midterm 1 Review | |
M, Feb 12 | Finite State Machines, Lab 4 | See tutorial. Direct link. |
W, Feb 14 | Counters, Integers, Lab 4, Cont. | See tutorial. Direct link. |
M, Feb 19 | FSMD |
See Controllers+Datapath section of VHDL tutorial. Fibonacci Calculator FSMD (1-process model) Fibonacci code and datapath |
W, Feb 21 | FSMD, FSM+D | See Controllers+Datapath section of VHDL tutorial. |
F, Feb 23 | FSM+D, Cont. |
See Controllers+Datapath section of VHDL tutorial. |
M, Feb 26 | Lab 6 | |
W, Feb 28 | Lab 6, Cont. | |
F, Mar 1 | Class Cancelled | |
M, Mar 12 | FPGA Architectures |
FPGA Architecture Slides
Max 10 Overview |
W, Mar 14 | FPGA Architectures, Cont. | |
F, Mar 16 | Midterm 2 Review | |
M, Mar 19 | MIPS (Arrays, RAM, Register File) |
Sample RAM Code Sample Register File Code |
W, Mar 21 | MIPS (Register File, ALU, Datapath) | |
F, Mar 23 | Midterm 2 | |
M, Mar 26 | MIPS (Memory, I/O Ports, Control, R-Type Instructions) | |
W, Mar 28 | MIPS (I-Type Instructions, Load/Store Instructions) | |
F, Mar 30 | MIPS (Load/Store Instructions, Jump Instructions) | |
M, April 2 | MIPS (Branch Instructions, Misc.) | |
W, April 4 | MIPS (MIF Files and assembly code) |
|
F, April 6 |
Midterm 2 Solution 2-process FSMD |
2-process FSMD code |
M, April 9 |
2-process FSMD, Cont. Buses, Tristates VHDL Arrays |
Bus/Tristate Code |
W, April 11 |
VHDL Arrays Research Overview |
Application case study example: A performance and energy comparison of FPGAs, GPUs, and multicores for sliding-window applications Intel Xeon+FPGA study: Scalable Window Generation for the Intel Broadwell+Arria 10 and High-Bandwidth FPGA Systems FPGA Virtualization study: Virtualization Slides Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing |
F, April 13 | Metastability, Clock-Domain Crossing |
Papers CDC overview |
M, April 16 | Metastability, Clock-Domain Crossing, Cont. | |
W, April 18 |
Pareto Optimality Design-space exploration |
|
F, April 20 |
Pareto Optimality Design-space exploration |
|
M, April 23 | Midterm 3 Review |