Midterm 1 will be on Friday, Feb 13 in class. Midterm 2 will be on Friday, March 20. Midterm 3 will be Wed, April 22. There is no final.
Advanced modular logic, design languages, finite state machines and binary logic.
This course will review basic concepts in digital logic (muxes, decoders,
encoders, etc.) and will build upon these concepts to form complex digital
circuits consisting of finite state machines, controllers, and datapaths. The
course will be lab intensive and will provide realistic case studies to apply
concepts learned during lecture. All concepts discussed in lecture will be
implemented in VHDL.
|W, January 7||Course Intro||
|F, January 9||VHDL Intro (guidelines, entity and architecture, basic mux implementation)||Tutorial|
|M, January 12||VHDL Intro (if vs. case, priority encoder, structural architectures)||
Tutorial (read combinational logic and structural description sections)
4x1 mux used in class
See Ch. 6 for priority encoder example.
|W, January 14||
Structural Architectures, Cont.
|F, January 16||Arithmetic Operations, Testbenches||
Add w/ carry examples in different packages:
std_logic_arith with std_logic_unsigned
|M, January 19||Holiday|
|W, January 21||Lab 2, Generics, Avoiding Latches|
|F, January 23||Carry-Lookahead Adders||Read Section 5.4|
|M, January 26||Lab 3, Configurations, For-generate|
|W, January 28||Lab 3 Cont., Constants, Initialization of Signals (Don't do it)|
|F, January 30||Synthesis of For Loops, If Statements, and Case Statements
|M, Feb 2||Sequential Logic||See tutorial.|
|W, Feb 4||Synthesis of Sequential Logic||See updated tutorial example.|
|F, Feb 6||Midterm 1 Review|
|M, Feb 9||Finite State Machines||See tutorial. Direct link.|
|W, Feb 11||Lab 4||F, Feb 13||Lab 4|
|M, February 16||FSMD||
See Controllers+Datapath section of VHDL tutorial.
Fibonacci Calculator FSMD (1-process model)
Fibonacci code and datapath
Exact code from class.
|W, Feb 18||FSM+D, Lab 5||F, Feb 20||Midterm 1 Discussion
|M, Feb 23||Lab 6||W, Feb 25||Lab 6, Cont.||F, Feb 27||Class Cancelled||M, Mar 9||Arrays, If Generate (see delay example on tutorial)|
|W, March 11||FPGA Architectures||
FPGA Architecture Slides
Cyclone II Datasheet
Cyclone II Figures
Cyclone II Family Overview
|F, March 13||FPGA Architectures, Cont.||
Cyclone III Family Handbook
Cyclone III Family Overview
|M, March 16||FPGA Architectures, Cont.|
|W, March 18||Midterm 2 Review|
|F, March 20||Midterm 2|
|M, March 23||Small 8 Intro, Buses, Tristates||Bus/Tristate Code|
|W, March 25||
Midterm 2 Discussion
Small 8 ALU, Internal Architecture, Ports
|F, March 27||Small8 Opcode Fetch|
|M, March 30||Small8 Instruction Set|
|W, April 1||Small8 instruction set, Cont.|
|F, April 3||
Small8 instruction Set, Cont.
Small8 sample programs
|M, April 6||Small8 sample programs, cont.|
|W, April 8||Metastability, Clock-Domain Crossing||Papers|
|F, April 10||
|M, April 13||
2-process FSMD code
|W, April 15||
|F, April 17||
Design-space exploration, cont.