We will also be using the Digilent Analog Discovery Board. If you have not purchased it yet, you can here: http://www.digilentinc.com/Products/Detail.cfm?Prod=ANALOG-DISCOVERY

Lab workarounds

• If you are using Quartus 9.1 and get an error about incremental compilation when using Signal Tap, do the following: add "set_global_assignment -name INCREMENTAL_COMPILATION OFF" to the .qsf file in the project folder. If incremental compilation is turned off and you get a license file error, it's likely because you added post-fit nodes instead of pre-synthesis nodes in Signal Tap.

Lab 0: (Week 2: Jan 12-16)

1. Obtain and test board in lab. If you have questions about the board, you can read the manual here.
2. Install latest free web edition of Quartus: Link
3. Read over the following tutorials (ignore references to lab assignment tasks. You will be using these tools as part of the next lab)
   • Oscillosope Tutorial
   • LSA Tutorial
   • Signal Tap Tutorial (ignore line ment ioning "Incremental Build")
   • Digilent Analog Discovery Getting Started
4. Review Quartus Tutorials 1 and 3 (Appendices in textbook)
5. Start reading the ModelSim tutorial. You do not need to finish the entire tutorial, but you will be using this tool all semester, so make sure you understand the basics. You can install a free version of Modelsim here. Select the ModelSim-Altera Starter Edition.

Lab 1: Introduction to EEL 4712 Digital Design Lab (Week 3: Jan 20-26)

• Lab Instructions
• VHDL Files
  
  
• Checklist

Lab 2: Generic-Width Behavioral ALU (Week 4: Jan 27-Feb 2)

• Lab Instructions
• Small sample testbench for alu_ns
• Top level entity

You will find these incredibly useful:

• VHDL Package Reference
• VHDL Math Tricks (Comparison of std_logic_arith and numeric_std)

• Lab 2 Checklist

Lab 3: Ripple-Carry and Carry-Lookahead Adders (Week 5: Feb3-Feb9)

• Lab Instructions
• Adder entity skeleton code
• Provided testbench
• Top-level entity

• Top-level for timing simulation
• Testench for timing simulation

• Lab 3 Checklist

Lab 4: Finite State Machines (Week 7: Feb17-Feb23)

• Lab Instructions
• All provided code

• Lab 4 Checklist

Lab 5: GCD Calculator (Week 8: Feb24-Mar9) The Monday lab finishes after Spring Break.

• Lab Instructions
• All provided code

• Lab 5 Checklist

Lab 6: VGA Interfacing (Week 9-10: March10-March23) The second week is optional for those that finish early. Everyone must attend the first week.

• Lab Instructions
• MIF file instructions
• All provided code

• Lab 6 Checklist

Lab 7: Small8 Microcontroller (3 weeks, Starts on Tuesday, March 31)

• Lab Instructions
• All provided material
• References for ALU status flags:
  • http://teaching.idallen.com/dat2343/10f/notes/040_overflow.txt
  • http://homepages.ius.edu/jfdoyle/c335/Html/Chapter3.htm
  • Carry flag explanation for substraction. See the a+not(b)+C discussion towards the bottom.