EEL4712 Digital Design (Spring 2013)


Previous Midterms

All pre-lab assignments are due before the beginning of your lab section. Please ignore the due date on Sakai. It was too much trouble to create 9 different assignments for each lab, so I listed the due date in the future. The TAs will check the actual submission date to determine if it is late. There is a 10% penalty per day for late submissions.

Midterm 1 will be on Friday, Feb 15 in class. Midterm 2 will be on Friday, March 22. Midterm 3 will be Wed, April 24. There is no final.

Labs will start on Monday, Jan 14. Lab 0 has already been posted (see the LABS link below). Due to the large number of tutorials, I would suggest starting early.

Catalog Description

Advanced modular logic, design languages, finite state machines and binary logic.


This course will review basic concepts in digital logic (muxes, decoders, encoders, etc.) and will build upon these concepts to form complex digital circuits consisting of finite state machines, controllers, and datapaths. The course will be lab intensive and will provide realistic case studies to apply concepts learned during lecture. All concepts discussed in lecture will be implemented in VHDL.

Course Information


Date Topic Slides/Reading Material
M, January 7 Course Intro Slides
W, January 9 VHDL Intro (guidelines, entity and architecture, basic mux implementation) Tutorial
F, January 11 VHDL Intro (if vs. case, priority encoder, structural architectures) Tutorial (read combinational logic and structural description sections)
4x1 mux used in class
See Ch. 6 for priority encoder example.
M, January 14 Arithmetic Operations in std_logic_arith and numeric_std Add w/ carry examples in different packages:
std_logic_arith with std_logic_unsigned

Common Problems:
Signal/variable comparison
W, January 16 Lab 1, Arithmetic Operations Cont. See lab website and code from previous lecture.
F, January 18 Arithmetic Operations Cont., Generics, Testbenches Read the combinational logic section of my tutorial, including the testbenches.
M, January 21 Holiday
W, January 23 Lab 2
F, January 25 Carry-Lookahead Adders Read Section 5.4
M, January 28 Testbenches, Cont.
Generate statements
for loops
See structural ripple-carry adder in my tutorial.
W, January 30 Lab 3
See lab page.
F, February 1 Sequential Logic See sequential logic tutorial.
M, February 4 Sequential Logic, Cont.
1-process Finite State Machines
See tutorial.
W, February 6 2-Process Finite State Machines
Lab 4
See tutorial and lab webpage.
F, February 8 Midterm Review
M, February 11 Class Cancelled
W, February 13 Class Cancelled
F, February 15 Midterm 1
M, February 18 Class Cancelled
W, February 20 FSMD See Controllers+Datapath section of VHDL tutorial.
Fibonacci Calculator FSMD (1-process model)
Fibonacci code and datapath
F, February 22 FSM+D See Controllers+Datapath section of VHDL tutorial.
M, February 25 Arrays, if generate See delay entity example in VHDL tutorial.
W, February 27 Midterm 1 Discussion, Lab 6 Intro
F, March 1 Lab 6 Discussion
M, Mar 11 FPGA Architectures FPGA Architecture Slides
Cyclone II Datasheet
Cyclone II Figures
Cyclone II Family Overview
W, Mar 13 FPGA Architectures, Cont.
F, Mar 15 FPGA Architectures, Cont.
M, Mar 18 Midterm 2 Review Slides on creating datapaths and controllers
W, Mar 20 Small 8 Intro, Buses, Tristates
2-process FSMD
Bus/Tristate Code
2-process FSMD code
F, Mar 22 Midterm 2
M, Mar 25 Small8: ALU, Buses, Ports Status Flags:Overview1 Overview2
W, Mar 27 Small8: ALU, Buses, Ports, Cont.
Arrays, Memories
Altera Guidelines for Memories (pg.12-35)
Xilinx Guidelines for Memories (pg.144-195)
F, Mar 29 Small8: Instruction Set
M, April 1 Small8: Instruction Set
W, April 3 Small8: Instruction Set
F, April 5 Small8: Instruction Set, MIF Files
M, April 8 Metastability, Clock-Domain Crossing Related papers
W, April 10 Metastability, Clock-Domain Crossing, Cont.
F, April 12 Design-space exploration, Pareto optimality
M, April 15 Design-space exploration, Pareto optimality
W, April 17 Pipelining Pipeline Example
Sliding-Window Paper
Sliding-Window Slides
F, April 19 Midterm 3 Review

VHDL Resources