Fundamental concepts at advanced undergraduate level (EEL4720) and introductory graduate level (EEL5721) in reconfigurable computing based upon advanced technologies in field-programmable logic devices. Topics include general concepts, device architectures, design tools, metrics and kernels, system architectures, and application case studies.
| Date | Topic | Slides/Reading Material |
|---|---|---|
| M, Aug 23 | Course info, Intro to RC |
Slides Overview Paper: Compton, Hauck Survey Motivating FPGA Example: Scalable Window Generation for the Intel Broadwell+Arria 10 and High-Bandwidth FPGA Systems Tutorial: Start reading "My VHDL Tutorial" under VHDL Resources. |
| W, Aug 25 | VHDL: Introduction, Combinational Logic |
See combinational logic section of "My VHDL Tutorial" under VHDL Resources. Lecture from previous semester |
| F, Aug 27 | VHDL: Combinational Logic, Cont. | See combinational logic section of "My VHDL Tutorial" under VHDL Resources. |
| M, Aug 30 | VHDL: Sequential Logic | See sequential logic section of "My VHDL Tutorial" under VHDL Resources. |
| W, Sep 1 | VHDL: Structural Architectures, Finite State Machines |
See my tutorial. Mux example used in class |
| F, Sep 3 | VHDL: Finite State Machines, FSMD, FSM+D |
See finite state machine section and controller+datapath section of tutorial. Additional FSMD example used in class |
| W, Sep 8 | VHDL: FSM+D, Testbenches, Lab 1 | GCD testbench from class |
| F, Sep 10 | Device Tradeoffs |
Slides Measuring the Gap between FPGAs and ASICs |
M, Sep 13 | Device Tradeoffs, Cont. FPGA Architectures |
Architecture Slides | W, Sep 15 | FPGA Architectures, Cont. |
F, Sep 17 | FPGA Architectures, Cont. |
M, Sep 20 | FPGA Architectures, Cont. Lab 2 |
| W, Sep 22 | Lab 2, Cont. | |
| F, Sep 24 | Optimization Problems | Slides |
| M, Sep 27 |
Optimization Problems, Cont. RT Synthesis, Placement, and Routing |
Slides
Papers: Placement/Routing, Pathfinder, Versatile Place+Route (VPR) |
| W, Sep 29 | RT Synthesis, Placement, and Routing, Cont. | |
| F, Oct 1 | Pipelining, Parallelism, Systolic Arrays | Pipelining Slides |
| M, Oct 4 | Pipelining, Parallelism, Systolic Arrays, Cont. | |
| W, Oct 6 | Lab 3, Midterm Review | |
| F, Oct 8 | No class | |
| M, Oct 11 | Midterm 1 | |
| W, Oct 13 | Pipelining, Cont. | |
| F, Oct 15 | Midterm 1 Solution | |
| M, Oct 18 |
Pipelining, Cont. VHDL: for-generate, if-generate Misc VHDL |
|
| W, Oct 20 | Lab 4 | |
| F, Oct 22 |
Misc VHDL Metastability, Clock-Domain Crossing |
Papers Basics of setup and hold time |
| M, Oct 25 | Metastability, Clock-Domain Crossing, Cont. | |
| W, Oct 27 |
Metastability, Clock-Domain Crossing, Cont. Debugging FPGA Problems |
|
| F, Oct 29 | Lab 5 | Lecture (skip to 20:30) |
| M, Nov 1 | High-level Synthesis |
High-level Synthesis Slides Lecture (022) |
| W, Nov 3 | High-level Synthesis, Cont. | Lecture (023) |
| F, Nov 5 | High-level Synthesis, Cont. | Lecture (024) |
| M, Nov 8 | High-level Synthesis, Cont. | Lecture (025) |
| W, Nov 10 | Buffering |
Buffering Slides
Paper 1 Paper 2 Sliding-Window Paper Sliding-Window Paper on Broadwell+Arria10 Lecture (028) |
| F, Nov 12 | Final Project (Overview) | Lecture (029) |
| M, Nov 15 | Final Project (Pipeline, user_app, signal/kernel buffers, wrapper) | Lecture (030) |
| W, Nov 17 | Final Project (wrapper, dram_rd, EDN files, dram_wr) | Lecture (031) |
| F, Nov 19 | Final Project (C++, control) | Lecture (032) |
| M, Nov 22 |
Final Project (testing suggestions) 2-process FSMD |
FSMD code Lecture (033) |
| M, Nov 29 |
2-process FSMD, Cont. Elastic IP |
FSMD Lecture (035) (only watch first 7 minutes) Lecture: Elastic IP |
| W, Dec 1 | FPGA Virtualization |
Lecture: Intermediate Fabrics Paper 1 Paper 2 |
| F, Dec 3 | Midterm 2 Review |
Lecture (36) |
| M, Dec 6 | UVM (Universal Verification Methodology) |
Overview Example |
| M, Dec 8 | Midterm 2 |