Fundamental concepts at advanced undergraduate level (EEL4720) and introductory graduate level (EEL5721) in reconfigurable computing based upon advanced technologies in field-programmable logic devices. Topics include general concepts, device architectures, design tools, metrics and kernels, system architectures, and application case studies.
| Date | Topic | Slides/Reading Material |
|---|---|---|
| W, Aug 21 | Course info, Intro to RC |
Slides Overview Paper: Compton, Hauck Survey Motivating FPGA Example: Scalable Window Generation for the Intel Broadwell+Arria 10 and High-Bandwidth FPGA Systems Tutorial: Start reading "My VHDL Tutorial" under VHDL Resources. |
| F, Aug 23 | VHDL Tutorial (Combinational Logic) | See combinational logic section of "My VHDL Tutorial" under VHDL Resources. |
| M, Aug 26 | VHDL Tutorial (Combinational Logic, Cont.) | See my tutorial. |
| W, Aug 28 | VHDL Tutorial (Sequential Logic) | See my tutorial. |
| F, Aug 30 | VHDL Tutorial (Sequential Logic, Cont., Structural Architectures) | See my tutorial. |
| M, Sep 2 | Holiday | |
| W, Sep 4 | Class Canceled (hurricane) | |
| F, Sep 6 | VHDL Tutorial (Finite-State Machines, FSMD, FSM+D) |
See finite state machine section and controller+datapath section of tutorial. Additional FSMD example used in class |
| M, Sep 9 | VHDL Tutorial (FSMD, FSM+D, Testbenches) Lab 1 |
|
| W, Sep 11 | VHDL Tutorial (Testbenches, Cont.) Device Tradeoffs |
Slides Measuring the Gap between FPGAs and ASICs |
F, Sep 13 | Device Tradeoffs, Cont. FPGA Architectures |
Architecture Slides | M, Sep 16 | FPGA Architectures, Cont. | W, Sep 18 |
FPGA Architectures, Cont. Lab 2 L3Harris Talk |
L3Harris Slides | F, Sep 20 | Lab 2, Cont. |
| M, Sep 23 | Optimization Problems | Slides |
| W, Sep 25 |
Optimization Problems, Cont. RT Synthesis, Placement, and Routing |
Slides
Papers: Placement/Routing, Pathfinder, Versatile Place+Route (VPR) |
| F, Sep 27 |
RT Synthesis, Placement, and Routing, Cont. Pipelining, Parallelism, Systolic Arrays |
Pipelining Slides |
| M, Sep 30 | Pipelining, Cont. | |
| W, Oct 2 | Midterm 1 Review | |
| F, Oct 4 | No Class (Homecoming) | |
| M, Oct 7 | Midterm 1 | |
| W, Oct 9 | Lab 3 | |
| F, Oct 11 |
Pipelining, Cont. VHDL: for-generate, if-generate |
|
| M, Oct 14 |
VHDL: for-generate, if-generate Lab 4 |
|
| W, Oct 16 |
Lab 4 High-Level Synthesis |
High-level Synthesis Slides |
| F, Oct 18 | High-Level Synthesis, Cont. | |
| M, Oct 21 | High-Level Synthesis, Cont. | |
| W, Oct 23 | High-Level Synthesis, Cont. | |
| F, Oct 25 | High-Level Synthesis, Cont. | |
| M, Oct 28 | Class Cancelled | |
| W, Oct 30 | Metastability, Clock-Domain Crossing |
Papers Basics of setup and hold time |
| F, Nov 1 |
Lab 5 Buffering |
Buffering Slides
Paper 1 Paper 2 Sliding-Window Paper Sliding-Window Paper on Broadwell+Arria10 |
| M, Nov 4 | Buffering, Cont. | |
| W, Nov 6 | Final Project (Overview) | |
| F, Nov 8 | Final Project (Pipeline, user_app, signal/kernel buffers, wrapper) | |
| W, Nov 13 | Final Project (wrapper, dram_rd, EDN files, dram_wr) | |
| F, Nov 16 | Final Project (C++, control) | |
| M, Nov 18 |
Final Project (testing suggestions) 2-process FSMD |
FSMD code |
| W, Nov 20 | Class Canceled | |
| F, Nov 22 | Stratix 10, HyperFlex | Slides |
| M, Nov 25 | Recursive Architectures | Slides |