The late penalty for all assignments is 10% per day. Anything more than 5 minutes late is one day late.
Fundamental concepts at advanced undergraduate level (EEL4720) and introductory graduate level (EEL5721) in reconfigurable computing based upon advanced technologies in field-programmable logic devices. Topics include general concepts, device architectures, design tools, metrics and kernels, system architectures, and application case studies.
Date | Topic | Slides/Reading Material |
---|---|---|
M, Aug 24 | Course info, Intro to RC |
Slides Paper: Compton, Hauck Survey Tutorials: Start reading "My Tutorial" under VHDL Resources. |
W, Aug 26 | VHDL Tutorial (Combinational Logic) | See combinational logic section of "My Tutorial" under VHDL Resources. |
F, Aug 28 | VHDL Tutorial (Combinational Logic, Sequential Logic) | See my tutorial. |
M, Aug 31 | VHDL Tutorial (Sequential Logic, Cont.) | See my tutorial. |
W, Aug Sep 2 | VHDL Tutorial (Sequential Logic, Cont., Finite-State Machines) | See my tutorial. |
F, Aug Sep 4 | VHDL Tutorial (Finite-State Machines, FSMD, Structural Architectures, FSM+D) |
See controller+datapath section of tutorial. Additional FSMD example used in class |
M, Sep 7 | Holiday | |
W, Sep 9 | Lab 1 | |
F, Sep 11 | Testbench overview Device Tradeoffs |
Slides Measuring the Gap between FPGAs and ASICs |
M, Sep 14 | Device Tradeoffs, Cont. FPGA Architectures |
Architecture Slides | W, Sep 16 | FPGA Architectures, Cont. | F, Sep 18 | FPGA Architectures, Cont. |
Xilinx 7 Series FPGA Overview Xilinx 7 Series CLB Architecture Zynq Product Table Architecture Slides (UPDATED) |
M, Sep 21 | FPGA Architectures, Cont. VHDL: for-generate |
W, Sep 23 | Lab 2 |
F, Sep 25 |
Lab 2, Cont. Optimization Problems |
Slides |
M Sep 28 | Optimization Problems, Cont. | |
W Sep 30 | Optimization Problems, Cont. RT Synthesis, Placement, and Routing |
Slides
Papers: Placement/Routing, Pathfinder, Versatile Place+Route (VPR) |
F Oct 2 | RT Synthesis, Placement, and Routing, Cont. Lab 3 |
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M, Oct 5 |
Lab 3, Cont. |
|
W, Oct 7 | Pipelining, Parallelism, Systolic Arrays | Pipelining Slides |
F, Oct 9 | Pipelining, Parallelism, Systolic Arrays, Cont. | |
M, Oct 12 | Midterm 1 Review | |
W, Oct 14 | Midterm 1 | |
F, Oct 16 | Lab 4 | |
M, Oct 19 |
Lab 4, Cont. Pipelining, Cont. |
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W, Oct 21 | High-level Synthesis | High-level Synthesis Slides |
F, Oct 23 | High-level Synthesis, Cont. | |
M, Oct 26 | High-level Synthesis, Cont. | |
W, Oct 28 | Midterm 1 Solution Discussion | |
F, Oct 30 | High-level Synthesis, Cont. | |
M, Nov 2 | Metastability, Clock-Domain Crossing | Papers |
W, Nov 4 |
Metastability, Clock-Domain Crossing, Cont. Lab 5 |
|
F, Nov 6 | No class | |
M, Nov 9 | High-level Synthesis, Cont. | |
W, Nov 11 | No class | |
F, Nov 13 | Final project (DMA interface) | |
M, Nov 16 | Buffering |
Buffering Slides
Paper 1 Paper 2 Sliding-Window Paper |
W, Nov 18 |
Buffering, Cont. Final project |
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F, Nov 20 | Final project | |
M, Nov 23 |
Final project (C++, memory map, testbench) High-level Synthesis limitations |
Extacting task-level parallelism |
M, Nov 30 | Hw/Sw Partitioning |
Slides
System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search An Evaluation of Bipartitioning Techniques |
F, Dec 4 | Midterm Review | |
M, Dec 7 |
FPGA Virtualization Fast Compilation OpenCL High-level Synthesis Appromxiation Computing |
OpenCL+Virtualization
Approximate Computing |