EEL4720/5721 Labs (Fall 2015)
Useful References
Common Vivado Problems:
- The following error is caused by using a project path that has spaces. The only known workaround is to use a different path.
ERROR: [Common 17-165] Too many positional options when parsing '-force', please type 'create_project -help' for usage info.
- If you add a VHDL file to an IP core and that file is already stored in the IP core's directory, do not check the box to copy the files into the repository. If you do check the box, Vivado will report an error that the file is already there and won't add the file to your project.
Lab 0 - Due Date: Sep 4 (Start Now!)
Lab Instructions
VHDL Files
Links:
Download Xilinx Vivado WebPACK (Make sure to get the WebPACK and not the full version)
Vivado tutorials:
Known Problems:
- If Vivado freezes during installation (e.g., while "verifying credentials"), try using the full installer instead of the web installer. There should be a tar file that is around 4.8 GB.
Lab 1 - Fibonacci Calculator (DUE SEP 21 11:59 PM)
Instructions
Make sure to read the controllers+datapaths section of my VHDL tutorial.
Lab 2 - ZedBoard Tutorial (DUE OCT 2, 11:59 PM)
Lab 3 - Fibonacci Calculator on ZedBoard (DUE OCT 12, 11:59PM) EXTENDED UNTIL OCT 15, 11:59PM
Lab 4 - Simple Pipeline (DUE OCT 30, 11:59 PM) EXTENDED UTNIL NOV. 2, 11:59PM
Lab 5 - Clock-domain crossing (DUE Nov 12, 11:59 PM)
Class Project - 1D Time-Domain Convolution (DUE December 6, 11:59PM) IMPORTANT: NO LATE SUBMISSIONS WILL BE ACCEPTED.