Changed due date of final project to Dec 7, 11:55 pm.
Midterm 2 has been moved to Monday, Dec 3. EDGE students will have from Dec 3-5.
Final project information updated with due date and potential problems.
Lab0 instructions have been updated to include a description of what files should be submitted
Tuesday office hours have changed to period 4 (10:40).
Fundamental concepts at advanced undergraduate level (EEL4720) and introductory graduate level (EEL5721) in reconfigurable computing based upon advanced technologies in field-programmable logic devices. Topics include general concepts, device architectures, design tools, metrics and kernels, system architectures, and application case studies.
| Date | Topic | Slides/Reading Material |
|---|---|---|
| W, Aug 22 | Course info, Intro to RC |
Slides Paper: Compton, Hauck Survey |
| F, Aug 24 | VHDL Tutorial, Combinational Logic |
Tutorial |
| M, Aug 27 | VHDL Tutorial, Combinational Logic | |
| W, Aug 29 | VHDL Tutorial, Sequential Logic, Structural Descriptions | |
| F, Aug 31 | VHDL Tutorial, FSMs, FSMDs, FSM+Ds | Lab 1 assigned, see lab page |
| W, Sep 5 | Device Comparisons | Slides |
| F, Sep 7 | RC Architectures |
Slides
Virtex 4 User Guide Virtex 5 User Guide |
| M, Sep 10 | RC Architectures, Cont. | |
| W, Sep 12 | RC Architectures, Cont. Testbench Discussion |
|
| F, Sep 14 | Nallatech Tutorial, Lab 2 | Nallatech Slides |
| M, Sep 17 | Optimization Problems | Slides |
| W, Sep 19 | RT Synthesis, Placement, and Routing |
Slides
Papers: Placement/Routing, Pathfinder, Versatile Place+Route (VPR) |
| F, Sep 21 | RT Synthesis, Placement, and Routing, Cont. For-generate VHDL statement |
|
| M, Sep 24 | Lab 3 | Lab 3 Discussion|
| W, Sep 26 | Pipelining, Parallelism, Systolic Arrays |
Slides
|
| F, Sep 28 | Pipelining, Parallelism, Systolic Arrays, Cont. |
Papers: A Quantitative Analysis of the Speedup Factors of FPGAs over Processors The Density Advantage of Configurable Computing |
| M, Oct 1 | Pipelining, Parallelism, Systolic Arrays, Cont. | |
| W, Oct 3 | Lab 4 | |
| F, Oct 5 | Midterm 1 Review | |
| M, Oct 8 | Lab 4 Glue Logic discussion, VHDL arrays | See delay example in my tutorial. |
| W, Oct 10 | Midterm 1 | |
| F, Oct 12 | Metastability, Clock-Domain Crossing | Papers |
| M, Oct 15 | Metastability, Clock-Domain Crossing, Lab 5 | |
| W, Oct 17 | Lab 5 | |
| F, Oct 19 | Midterm 1 Discussion, Buffering |
Slides
Paper 1 Paper 2 |
| M, Oct 22 | Buffering, Cont. | Sliding-Window Paper |
| W, Oct 24 | Final Project Discussion | |
| F, Oct 26 | Final Project Discussion (SRAM Interfaces) | |
| M, Oct 29 | Final Project Discussion (Pipeline, Signal Buffer, Kernel Buffer) | |
| W, Oct 31 | High-level Synthesis | Slides |
| F, Nov 2 | High-level Synthesis, Cont. | |
| M, Nov 5 | High-level Synthesis, Cont. | |
| W, Nov 7 | High-level Synthesis, Cont. | |
| W, Nov 14 | High-level Synthesis, Cont. | |
| F, Nov 16 | High-level Synthesis, Cont. Hw/Sw Partitioning |
Hw/Sw Partitioning Slides
System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search An Evaluation of Bipartitioning Techniques |
| M, Nov 26 |
Hw/Sw Partitioning, Cont. 2-process FSMD examples |
2-process FSMD code |
| W, Nov 28 | 2-process FSMD examples | |
| F, Nov 30 | Midterm Review |