[Main Page] [Curriculum Vitae]

Patents

  1. G. Stitt, D. Campbell, R. Aloni, T. Vaseliou, J. Salkey. Architecture-Independent Approximation Discovery. Serial No. 62/527,667; filed June 30, 2017. UF#-16791
  2. K. Yang. K. Robert, S. Bhunia, G. Stitt. A Uniquified FPGA Virtualization Approach to Hardward Security, Filed 12/13/2016, UF# 16477
  3. J. Coole and G. Stitt. Overlay Architecture For Programing FPGAs. Filed 4/29/2016, U.S. Provisional App. No.: 62/329,944; UF# 16190
  4. G. Stitt and J. Wernsing. Elastic Computing. Filed 04/11/11, UF#-13728, 222106-8135, Patent Application Serial No. 61/474,020.
  5. F. Vahid, R. Lysecky, and G. Stitt. Warp processor for dynamic hardware/software partitioning, US Patent 7,356,672, 2008.

Journal Publications

  1. A. Landy and G. Stitt, “Serial arithmetic strategies for improving fpga throughput,” ACM Trans. Embed. Comput. Syst., vol. 16, pp. 84:1–84:25, July 2017.
  2. G. Stitt, R. Karam, K. Yang, and S. Bhunia, “A uniquified virtualization approach to hardware security,” IEEE Embedded Systems Letters, vol. 9, pp. 53-56, September 2017.
  3. D. Wilson and G. Stitt, “A scalable, low-overhead finite-state machine overlay for rapid FPGA application development,” CoRR, vol. abs/1705.02732, February 2017.
  4. G. Stitt, E. Schwartz, and P. Cooke, “A parallel sliding-window generator for high-performance digital-signal processing on fpgas,” ACM Trans. Reconfigurable Technol. Syst., vol. 9, pp. 23:1–23:22, May 2016.
  5. D. Wilson and G. Stitt, “The unified accumulator architecture: A configurable, portable, and extensible floating-point accumulator,” ACM Trans. Reconfigurable Technol. Syst., vol. 9, pp. 21:1–21:23, May 2016.
  6. G. Wang, G. Stitt, H. Lam, and A. George, “Core-level modeling and frequency prediction for dsp applications on fpgas,” International Journal of Rec, p. 20, 2015.
  7. R. Kirchgessner, A. D. George, and G. Stitt, “Low-overhead fpga middleware for application portability and productivity,” ACM Trans. Reconfigurable Technol. Syst., vol. 8, pp. 21:1–21:22, September 2015.
  8. P. Cooke, J. Fowers, G. Brown, and G. Stitt, “A tradeoff analysis of fpgas, gpus, and multicores for sliding-window applications,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 8, pp. 2:1–2:24, Mar 2015.
  9. P. Cooke, L. Hao, and G. Stitt, “Finite-state-machine overlay architectures for fast fpga compilation and application portability,” ACM Transactions on Embedded Computing Systems (TECS), vol. 1, p. 25, 2014.
  10. J. Coole and G. Stitt, “Fast, flexible high-level synthesis from opencl using reconfiguration contexts,” Micro, IEEE, vol. 34, pp. 42-53, Jan 2014.
  11. J. Fowers, G. Brown, J. Wernsing, and G. Stitt, “A performance and energy comparison of convolution on GPUs, FPGAs, and multicore processors,” ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers, vol. 9, pp. 25:1–25:21, January 2013.
  12. L. Hao and G. Stitt, “Bandwidth-sensitivity-aware arbitration for FPGAs,” Embedded Systems Letters, IEEE, vol. 4, pp. 73-76, September 2012.
  13. J. R. Wernsing and G. Stitt, “Elastic computing: A portable optimization framework for hybrid computers,” Parallel Computing, vol. 38, pp. 438–464, August 2012.
  14. C. Reardon, B. Holland, A. D. George, G. Stitt, and H. Lam, “Rcml: An environment for estimation modeling of reconfigurable computing systems,” ACM Transactions on Embedded Computing Systems (TECS): Special Section on CAPA’09, vol. 11, pp. 43:1–43:22, August 2012.
  15. A. George, H. Lam, and G. Stitt, “Novo-g: at the forefront of scalable reconfigurable supercomputing,” IEEE Computing in Science and Engineering Magazine, pp. 82–86, Jan/Feb 2011.
  16. G. Stitt, A. George, H. Lam, M. Smith, V. Aggarwal, G. Wang, C. Reardon, B. Holland, S. Koehler, and J. Coole, “An end-to-end tool flow for FPGA-accelerated scientific computing,” IEEE Design&Test of Computers: Special Issue on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing, vol. 28, pp. 68-77, July/August 2011.
  17. G. Stitt, “Are field-programmable gate arrays ready for the mainstream? ,” Micro, IEEE, vol. 31, pp. 58-63, Nov/Dec 2011.
  18. G. Stitt and J. Coole, “Intermediate fabrics: Virtual architectures for near-instant FPGA compilation,” Embedded Systems Letters, IEEE, vol. 3, pp. 81 -84, sept. 2011.
  19. J. Curreri, G. Stitt, and A. George, “High-level synthesis of in-circuit assertions for verification, debugging, and timing analysis,” International Journal of Reconfigurable Computing, vol. 2011, pp. 1-17, December 2011.
  20. S. Koehler, G. Stitt, and A. George, “Platform-aware bottleneck detection for reconfigurable computing applications,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 4, pp. 30:1–30:28, August 2011.
  21. V. Aggarwal, G. Stitt, A. George, and C. Yoon, “SCF: A framework for task-level coordination in reconfigurable, heterogeneous systems,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 2011, pp. 1-24, June 2011.
  22. G. Stitt and F. Vahid, “Thread warping: Dynamic and transparent synthesis of thread accelerators,” ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 16, pp. 32:1–32:21, June 2011.
  23. J. Coole and G. Stitt, “Traversal caches: A framework for FPGA acceleration of pointer data structures,” International Journal of Reconfigurable Computing, vol. 2010, pp. 1-16, December 2010.
  24. F. Vahid, G. Stitt, and R. Lysecky, “Warp processing: Dynamic translation of binaries to FPGA circuits,” Computer, vol. 41, pp. 40-46, July 2008.
  25. G. Stitt and F. Vahid, “Binary synthesis,” ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 12, pp. 1–30, August 2007.
  26. R. Lysecky, G. Stitt, and F. Vahid, “Warp processors,” ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 11, pp. 659–681, June 2006.
  27. G. Stitt, F. Vahid, and S. Nematbakhsh, “Energy savings and speedups from partitioning critical software loops to hardware in embedded systems,” ACM Transactions on Embedded Computing Systems (TECS), vol. 3, pp. 218–232, February 2004.
  28. F. Vahid, R. Lysecky, C. Zhang, and G. Stitt, “Highly configurable platforms for embedded computing systems,” Microelectronics Journal, vol. 34, pp. 1025 - 1029, November 2003. IEEE Workshop on Embedded System Codesign (ESCODES).
  29. J. Villarreal, D. Suresh, G. Stitt, F. Vahid, and W. Najjar, “Improving software performance with configurable logic,” Kluwer Journal on Design Automation of Embedded Systems, vol. 7, pp. 325–339, November 2002.
  30. G. Stitt and F. Vahid, “Energy advantages of microprocessor platforms with on-chip configurable logic,” IEEE Design & Test, vol. 19, pp. 36–43, November 2002.
  31. F. Vahid, R. Patel, and G. Stitt, “Propagating constants past software to hardware peripherals in fixed-application embedded systems,” ACM SIGARCH Computer Architecture News, vol. 29, pp. 25–30, December 2001. Selected for special issue from earlier version of paper in Compilers and Operating Systems for Low Power (COLP’01).

Conference Publications

  1. M. N. Emas, A. Baylis, and G. Stitt, “High-frequency absorption-fifo pipelining for stratix 10 hyperflex,” in The 26th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), April 2018.
  2. G. Stitt, A. Gupta, M. N. Emas, D. Wilson, and A. Baylis, “Scalable window generation for the intel broadwell+arria 10 and high-bandwidth fpga systems,” in Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA ’18, pp. 173–182, February 2018.
  3. C. Pascoe, S. Chenna, G. Stitt, and H. Lam, “A fpga-pipelined approach for accelerated discrete-event simulation of hpc systems,” in Heterogeneous High-performance Reconfigurable Computing (H2RC), p. 2, November 2017.
  4. A. Baylis, G. Stitt, and A. Gordon-Ross, “Overlay-based side-channel countermeasures: A case study on correlated noise generation,” in 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1308-1311, August 2017.
  5. D. Wilson and G. Stitt, “A scalable, low-overhead finite-state machine overlay for rapid fpga application development,” in International Workshop on Overlay Architectures for FPGAs (OLAF), co-located with FPGA 2017, February 2017.
  6. N. Kumar, C. Pascoe, C. Hajas, H. Lam, G. Stitt, and A. George, “Behavioral emulation for scalable design-space exploration of algorithms and architectures,” in International Conference on High Performance Computing, pp. 5-17, 2016.
  7. C. Pascoe, N. Kumar, H. Lam, and G. Stitt, “Fpga-pipelined discrete-event simulations for accelerated behavioral emulation of extreme-scale systems,” in Workshop on Modeling & Simulation of Systems & Applications (ModSim), 2016.
  8. N. Kumar, A. George, H. Lam, G. Stitt, and S. Hammond, “Understanding performance and reliability trade-offs for extreme-scale systems using behavioral emulation,” in Workshop on Modeling & Simulation of Systems and Applications (ModSim), 2015.
  9. A. Shastri, G. Stitt, and E. Riccio, “A scheduling and binding heuristic for high-level synthesis of fault-tolerant fpga applications,” in Application-specific Systems, Architectures and Processors (ASAP), 2015 IEEE 26th International Conference on, pp. 202-209, July 2015.
  10. D. Rudolph and G. Stitt, “An interpolation-based approach to multi-parameter performance modeling for heterogeneous systems,” in Application-specific Systems, Architectures and Processors (ASAP), 2015 IEEE 26th International Conference on, pp. 174-180, July 2015.
  11. J. Coole and G. Stitt, “Adjustable-cost overlays for runtime compilation,” in Field-Programmable Custom Computing Machines (FCCM), 2015 IEEE 23rd Annual International Symposium on, pp. 21-24, May 2015.
  12. A. Landy and G. Stitt, “Revisiting serial arithmetic: A performance and tradeoff analysis for parallel applications on modern fpgas,” in Field-Programmable Custom Computing Machines (FCCM), 2015 IEEE 23rd Annual International Symposium on, pp. 9-16, May 2015.
  13. J. Fowers, J. Liu, and G. Stitt, “A framework for dynamic parallelization of fpga-accelerated applications,” in Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems, SCOPES ’14, pp. 1–10, 2014.
  14. J. Fowers, K. Ovtcharov, K. Strauss, E. S. Chung, and G. Stitt, “A high memory bandwidth fpga accelerator for sparse matrix-vector multiplication,” in Proceedings of the 2014 IEEE 22nd International Symposium on Field-Programmable Custom Computing Machines, FCCM ’14, pp. 36–43, 2014.
  15. J. Coole and G. Stitt, “Opencl high-level synthesis for mainstream fpga acceleration,” in Workshop on SoCs, Heterogeneous Architectures and Workloads (SHAW), feb 2014.
  16. A. Landy and G. Stitt, “Pseudo-constant logic optimization,” in Application-Specific Systems, Architectures and Processors (ASAP), 2013 IEEE 24th International Conference on, pp. 99-102, June 2013.
  17. P. Cooke, J. Fowers, G. Stitt, and L. Hunt, “A comparison of correntropy-based feature tracking on fpgas and gpus,” in Application-Specific Systems, Architectures and Processors (ASAP), 2013 IEEE 24th International Conference on, pp. 237-240, June 2013.
  18. L. Hao and G. Stitt, “Virtual finite-state-machine architectures for fast compilation and portability,” in Application-Specific Systems, Architectures and Processors (ASAP), 2013 IEEE 24th International Conference on, pp. 91-94, June 2013.
  19. J. Fowers and G. Stitt, “Dynafuse: dynamic dependence analysis for FPGA pipeline fusion and locality optimizations,” in Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays, FPGA ’13, pp. 201–210, February 2013.
  20. A. Landy and G. Stitt, “A low-overhead interconnect architecture for virtual reconfigurable fabrics,” in CASES’12: Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems, CASES ’12, pp. 111–120, October 2012.
  21. J. R. Wernsing, G. Stitt, and J. Fowers, “The racecar heuristic for automatic function specialization on multi-core heterogeneous systems,” in CASES’12: Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems, CASES ’12, pp. 81–90, October 2012.
  22. J. Coole and G. Stitt, “BPR: fast FPGA placement and routing using macroblocks,” in CODES+ISSS’12: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES+ISSS ’12, pp. 275–284, October 2012.
  23. J. Curreri, G. Stitt, and A. George, “Communication visualization for bottleneck detection of high-level synthesis applications,” in FPGA ’12: Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays, FPGA ’12, pp. 33–36, February 2012.
  24. J. R. Wernsing and G. Stitt, “Racecar: a heuristic for automatic function specialization on multi-core heterogeneous systems,” in PPoPP ’12: Proceedings of the 17th ACM SIGPLAN symposium on Principles and Practice of Parallel Programming, PPoPP ’12, pp. 321–322, February 2012.
  25. R. Kirchgessner, G. Stitt, A. George, and H. Lam, “VirtualRC: a virtual FPGA platform for applications and tools portability,” in FPGA ’12: Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays, FPGA ’12, pp. 205–208, February 2012.
  26. J. Fowers, G. Brown, P. Cooke, and G. Stitt, “A performance and energy comparison of FPGAs, GPUs, and multicores for sliding-window applications,” in FPGA ’12: Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays, FPGA ’12, pp. 47–56, February 2012.
  27. V. Aggarwal, C. Yoon, A. George, H. Lam, and G. Stitt, “Performance modeling for multilevel communication in shmem+,” in PGAS’10: Proceedings of the Conference on Partitioned Global Address Space Programming Model, p. 10, October 2010.
  28. J. Wernsing and G. Stitt, “A scalable performance prediction heuristic for implementation planning on heterogeneous systems,” in ESTIMedia’10: 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, pp. 71-80, October 2010.
  29. J. Coole and G. Stitt, “Intermediate fabrics: Virtual architectures for circuit portability and fast placement and routing,” in CODES/ISSS ’10: Proceedings of the IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, pp. 13–22, October 2010.
  30. A. George, H. Lam, C. Pascoe, A. Lawande, and G. Stitt, “Novo-g: A view at the hpc crossroads for scientific computing,” in ERSA’10: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, July 2010.
  31. C. Reardon, A. George, G. Stitt, and H. Lam, “An automated scheduling and partitioning algorithm for scalable rc systems,” in ERSA’10: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, July 2010.
  32. J. Wernsing and G. Stitt, “Elastic computing: A framework for transparent, portable, and adaptive multi-core heterogeneous computing,” in LCTES ’10: Proceedings of the 2010 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, pp. 115–124, April 2010.
  33. J. Curreri, G. Stitt, and A. George, “High-level synthesis techniques for in-circuit assertion-based verification,” in RAW ’10: Proceedings of the 17th Reconfigurable Architectures Workshop, April 2010.
  34. J. Coole, J. Wernsing, and G. Stitt, “A traversal cache framework for fpga acceleration of pointer data structures: A case study on barnes-hut n-body simulation,” in Reconfigurable Computing and FPGAs, 2009. ReConFig ’09. International Conference on, pp. 143-148, Dec. 2009.
  35. V. Aggarwal, A. George, K. Yalamanchili, C. Yoon, H. Lam, and G. Stitt, “Bridging parallel and reconfigurable computing with multilevel pgas and shmem+,” in HPRCTA ’09: Proceedings of the Third International Workshop on High-Performance Reconfigurable Computing Technology and Applications, pp. 47–54, November 2009.
  36. V. Aggarwal, R. Garcia, G. Stitt, A. George, and H. Lam, “Scf: a device- and language-independent task coordination framework for reconfigurable, heterogeneous systems,” in HPRCTA ’09: Proceedings of the Third International Workshop on High-Performance Reconfigurable Computing Technology and Applications, pp. 19–28, November 2009.
  37. G. Wang, G. Stitt, H. Lam, and A. D. George, “A framework for core-level modeling and design of reconfigurable computing algorithms,” in HPRCTA ’09: Proceedings of the Third International Workshop on High-Performance Reconfigurable Computing Technology and Applications, pp. 29–38, November 2009.
  38. G. Stitt, G. Chaudhari, and J. Coole, “Traversal caches: a first step towards FPGA acceleration of pointer-based data structures,” in CODES/ISSS ’08: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, pp. 61–66, October 2008.
  39. S. Merchant, B. Holland, C. Reardon, A. George, H. Lam, G. Stitt, M. Smith, N. Alam, I. Gonzalez, E. El-Araby, P. Saha, T. El-Ghazawi, and H. Simmler, “Strategic challenges for application development productivity in reconfigurable computing,” in IEEE National Aerospace and Electronics Conference (NAECON), July 2008.
  40. I. Gonzalez, E. El-Araby, P. Saha, T. El-Ghazawi, H. Simmler, S. Merchant, B. Holland, C. Reardon, A. George, H. Lam, G. Stitt, N. Alam, and M. Smith, “Classification of application development for FPGA-based systems,” in IEEE National Aerospace and Electronics Conference (NAECON), July 2008.
  41. G. Stitt and J. Villarreal, “Recursion flattening,” in GLSVLSI ’08: Proceedings of the 18th ACM Great Lakes symposium on VLSI, pp. 131–134, May 2008.
  42. G. Stitt, “Hardware/software partitioning with multi-version implementation exploration,” in GLSVLSI ’08: Proceedings of the 18th ACM Great Lakes symposium on VLSI, pp. 143–146, May 2008.
  43. S. Sirowy, G. Stitt, and F. Vahid, “C is for circuits: capturing FPGA circuits as sequential code for portability,” in FPGA ’08: Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, pp. 117–126, February 2008.
  44. G. Stitt and F. Vahid, “Thread warping: a framework for dynamic synthesis of thread accelerators,” in CODES+ISSS ’07: Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, pp. 93–98, October 2007.
  45. G. Stitt, F. Vahid, and W. Najjar, “A code refinement methodology for performance-improved synthesis from C,” in ICCAD ’06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, pp. 716–723, November 2006.
  46. G. Stitt and F. Vahid, “New decompilation techniques for binary-level co-processor generation,” in ICCAD ’05: Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, pp. 547–554, November 2005.
  47. G. Stitt, F. Vahid, G. McGregor, and B. Einloth, “Hardware/software partitioning of software binaries: a case study of h.264 decode,” in CODES+ISSS ’05: Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pp. 285–290, September 2005.
  48. G. Stitt and F. Vahid, “A decompilation approach to partitioning software for microprocessor/FPGA platforms,” in DATE ’05: Proceedings of the conference on Design, Automation and Test in Europe, pp. 396–397, March 2005.
  49. G. Stitt, Z. Guo, W. Najjar, and F. Vahid, “Techniques for synthesizing binaries to an advanced register/memory structure,” in FPGA ’05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, pp. 118–124, February 2005.
  50. G. Stitt, R. Lysecky, and F. Vahid, “Dynamic hardware/software partitioning: a first approach,” in DAC ’03: Proceedings of the 40th conference on Design automation, pp. 250–255, June 2003.
  51. D. C. Suresh, W. A. Najjar, F. Vahid, J. R. Villarreal, and G. Stitt, “Profiling tools for hardware/software partitioning of embedded applications,” in LCTES ’03: Proceedings of the 2003 ACM SIGPLAN conference on Languages, compilers, and tools for embedded systems, pp. 189–198, June 2003.
  52. G. Stitt and F. Vahid, “Hardware/software partitioning of software binaries,” in ICCAD ’02: Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, pp. 164–170, November 2002.
  53. B. Grattan, G. Stitt, and F. Vahid, “Codesign-extended applications,” in CODES ’02: Proceedings of the tenth international symposium on Hardware/software codesign, pp. 1–6, May 2002.
  54. G. Stitt, B. Grattan, J. Villarreal, and F. Vahid, “Using on-chip configurable logic to reduce embedded system software energy,” in FCCM ’02: Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 143–151, April 2002.
  55. G. Stitt, F. Vahid, T. Givargis, and R. Lysecky, “A first-step towards an architecture tuning methodology for low power,” in CASES ’00: Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems, pp. 187–192, November 2000.

Technical Reports

  1. G. Stitt and F. Vahid, “Binary-level hardware/software partitioning of MediaBench, NetBench, and EEMBC benchmarks,” Tech. Rep. UCR-CSE-03-01, University of California, Riverside, January 2003.
[Main Page] [Curriculum Vitae]