The objectives of this course are to learn, understand, and extend existing design techniques for FPGAs and other reconfigurable devices. Specific goals include gaining experience with advanced pipelining strategies, techniques for creating scalable, high-frequency pipelines, experience with FPGA virtualization strategies and high-level synthesis tools, while also evaluating FPGA application studies in embedded and high-performance domains.
| Date | Topic | Slides/Reading Material |
|---|---|---|
| W, Jan 5 | Course info, Intro to RC |
Slides Start reading my SystemVerilog tutorial. |
| F, Jan 7 | SystemVerilog: Combinational Logic (Basic constructs, 2x1 mux) | Github Repo |
| M, Jan 10 | SystemVerilog: Combinational Logic, Cont. (2x1 mux, 4-input priority encoder) | |
| W, Jan 12 | SystemVerilog: Combinational Logic, Cont. (Parameterized priority encoder) | |
| F, Jan 14 | SystemVerilog: Combinational Logic, Cont. (Adder) | |
| M, Jan 17 | Holiday | |
| W, Jan 19 |
SystemVerilog: Combinational Logic, Cont. (Multiplier, ALU) |
|
| F, Jan 21 |
SystemVerilog: Combinational Logic, Cont. (ALU, Misc.) SystemVerilog: Structural Architectures |
Github repo for structural architectures |
| M, Jan 24 |
SystemVerilog: Sequential Logic |
Github repo for sequential logic Blocking vs. Non-blocking assignments |
| W, Jan 26 |
SystemVerilog: Sequential Logic, Cont. |
|
| F, Jan 28 |
SystemVerilog: Finite State Machines |
Github repo for FSMs FSM Design & Synthesis using SystemVerilog |
| M, Jan 31 | SystemVerilog: Finite State Machines, Cont. | |
| W, Feb 2 | SystemVerilog: Finite State Machines and Datapaths (FSMDs) | Github repo for FSMs + Datapaths |
| F, Feb 4 | SystemVerilog: FSMDs, FSM+Ds | |
| M, Feb 7 | SystemVerilog: FSMDs, FSM+Ds, Cont. | |
| W, Feb 9 | SystemVerilog: FSM+Ds, Cont. | |
| F, Feb 11 |
SystemVerilog: FSM+Ds, Cont. if/case generate |
|
| M, Feb 14 | SystemVerilog: for generate, unpacked arrays, parameter verification | |
| W, Feb 16 | SystemVerilog: parameter verification, gotchas | Github repo for SV gotchas |
| F, Feb 18 | Midterm 1 Review | |
| M, Feb 21 |
Lab servers SV testbenches: basic mux example |
Information on using lab servers Github repo for basic testbenches |
| W, Feb 23 | SV testbenches: basic examples, race conditions | Race condition examples |
| F, Feb 25 | Midterm 1 | |
| M, Feb 28 |
Midterm 1 Solution SV testbenches: basic examples, race conditions, cont. |
|
| W, Mar 2 | SV testbenches: reset race conditions, basic register testbench. | |
| F, Mar 4 | SV testbenches: assertions, implication |
Github repo Doulos assertions tutorial |
| M, Mar 14 | SV testbenches: assertions, implication, cont. | |
| W, Mar 16 | SV testbenches: assertions, implication, cont. | |
| F, Mar 18 |
SV testbenches: assertions, implication, cont. SV testbenches: coverage (cover properties) |
Coverage examples |
| M, Mar 21 |
SV testbenches: coverpoints, covergroups |
|
| W, Mar 23 | SV testbenches: constrained-random verification (CRV) | CRV examples |
| F, Mar 25 | SV testbenches: constrained-random verification (CRV), Cont. | |
| M, Mar 28 |
SV testbenches: constrained-random verification (CRV), Cont. |
|
| W, Mar 30 |
SV testbenches: constrained-random verification (CRV), Cont. |
|
| F, April 1 |
Lab 2 UVM Timing analysis background |
UVM tutorial UVM Hello World EDA Playground UVM Examples Github repo for timing optimization (includes slides) |
| M, April 4 | Timing optimizations | Slides |
| W, April 6 |
Timing optimizations, cont. Timing analyzer tutorial |
|
| F, April 8 |
Timing analyzer tutorial, cont. Timing optimization examples |
|
| M, April 11 | Timing optimization examples | |
| W, April 13 | Timing optimization examples | |
| F, April 15 |
Timing optimization examples Lab 3 |
|
| M, April 18 | Final Review | |
| M, April 20 | Scalable Design Strategies |