EEL4712 Digital Design (Spring 2021)

Announcements

Midterm 1 will be on Friday, Feb 26 (delayed by 1 week). Midterm 2 will be on Friday, March 26 (delayed 1 week). Midterm 3 will be Wed, April 21. There is no final.

Late penalties for labs are 20% for the first day and 10% for each additional day.

Previous Midterms

Catalog Description

Advanced modular logic, design languages, finite state machines and binary logic.

Overview

This course will review basic concepts in digital logic (muxes, decoders, encoders, etc.) and will build upon these concepts to form complex digital circuits consisting of finite state machines, controllers, and datapaths. The course will be lab intensive and will provide realistic case studies to apply concepts learned during lecture. All concepts discussed in lecture will be implemented in VHDL.

Course Information

Lectures


Date Topic Slides/Reading Material
M, January 11 Course Intro Slides
Lecture Video (lecture1.mp4)
Additional Course Intro (class_intro.mp4)
W, January 13 VHDL Intro (guidelines, entity and architecture, basic mux implementation) Lecture (Part 1) (vhdl_intro.mp4)
Lecture (Part 2) (vhdl_intro2.mp4)
VHDL Tutorial (See 2x1 mux example)
F, January 15 VHDL Intro (if vs. case, priority encoder, structural architectures) Lecture (vhdl_intro3.mp4)
Tutorial (read combinational logic and structural description sections)
4x1 mux
See Ch. 6 for priority encoder example.
M, January 18 Holiday
W, January 20 Lab 1 Lecture (lab1.mp4)
See lab page.
F, January 22 Arithmetic Operations Lecture (vhdl_arithmetic_ops.mp4)
Add w/ carry examples in different packages:
numeric_std
std_logic_arith with std_logic_unsigned
std_logic_arith

Common Problems:
Signal/variable comparison
M, January 25 Generics, ALU, Latches Lecture (vhdl_alu.mp4)
See ALU example on my tutorial.
W, January 27 Lab 2 Lecture (lab2.mp4)
See lab website.
F, January 29 Testbenches Lecture (vhdl_testbenches.mp4)
See tutorial for examples.
M, February 1 Carry-Lookahead Adders Lecture (cla.mp4)
Carry-Lookahead Slides
Read Section 5.4
W, February 3 Lab 3, for-generate Lecture (lab3.mp4)
Lecture (vhdl-for-generate.mp4)
F, February 5 Sequential Logic Lecture (vhdl-sequential.mp4)
M, Feb 8 Sequential Logic, Cont.
Finite State Machines
Lecture (vhdl-fsm.mp4)
W, Feb 10 Lab 4 Lecture (lab4.mp4)
F, Feb 12 Misc VHDL, Sequential Logic Testbenches, Counters, Integers Lecture (vhdl-misc.mp4)
See tutorial. Counter link.
M, Feb 15 Counters Cont., FSMD Lecture (vhdl-fsmd.mp4)
See Controllers+Datapath section of VHDL tutorial.
Fibonacci Calculator FSMD (1-process model)
Fibonacci code and datapath
W, Feb 17 FSM+D Lecture (vhdl-fsm-plus-d.mp4)
See Controllers+Datapath section of VHDL tutorial.
Fibonacci Calculator FSMD (1-process model)
Fibonacci code and datapath
F, Feb 19 FSM+D, Cont.
Midterm 1 Review
FSM+D Part2 (vhdl-fsm-plus-d2.mp4)
Midterm Review (midterm1-review.mp4)
M, Feb 22 Lab 5, 2-process FSMD Lecture (lab5-vhdl-2p-fmsd.mp4)
2-process FSMD code
W, Feb 24 Recharge Day
F, Feb 26 Midterm 1
M, Mar 1 VGA, Lab 6 Lecture (lab6.mp4)
VGA Interface Slides
Lab 6 Slides
W, Mar 3 Lab 6, Cont.
Midterm 1 Solution
Lab 6 Part 2 (lab6_2.mp4)
Midterm 1 Solution (midterm1_solution.mp4)
F, Mar 5 FPGA Architectures Lecture
FPGA Architecture Slides
Max 10 Overview
M, Mar 8 FPGA Architectures, Cont. Lecture
W, Mar 10 FPGA Architectures, Cont. Lecture
F, Mar 12 Arrays, RAM, Register Files Lecture
M, Mar 15 MIPS (Register File, ALU, Datapath) Lecture
W, Mar 17 MIPS (Memory, I/O Ports, Instruction Fetch, Instruction Decode, Register Fetch) Lecture
F, Mar 19 MIPS (R-type Instructions) Lecture
M, Mar 22 Midterm 2 Review
W, Mar 24 Recharge Day
F, Mar 26 Midterm 2
M, Mar 29 MIPS (I-type, Jump, Branch, Load/Store) Lecture (I-type)
Lecture (Jump and Branch)
Lecture (Load and Store)
W, Mar 31 MIPS (MIF and Assembly Code) Lecture
F, April 2 Buses, Tristates Bus/Tristate Code
Lecture
M, April 5 Metastability, Clock-Domain Crossing Papers
CDC overview
Lecture
W, April 7 Metastability, Clock-Domain Crossing, Cont. Lecture
F, April 9 Design-Space Exploration, Pareto-Optimality Lecture
M, April 12 Design-Space Exploration, Pareto-Optimality, Cont. Lecture
W, April 14 Timing Optimization (Optional, will not be on tes Lecture: Background and Challenges
Lecture: Optimization Strategies
Github repo with code and slides
F, April 16 Midterm 3 Review
M, April 19 Efficient Processing of Deep Neural Network Lecture
Slides
W, April 21 Midterm 3

VHDL Resources