Midterm 1 will be on Friday, Feb 12 in class. Midterm 2 will be on Friday, March 18. Midterm 3 will be Wed, April 20. There is no final.
Advanced modular logic, design languages, finite state machines and binary logic.
This course will review basic concepts in digital logic (muxes, decoders,
encoders, etc.) and will build upon these concepts to form complex digital
circuits consisting of finite state machines, controllers, and datapaths. The
course will be lab intensive and will provide realistic case studies to apply
concepts learned during lecture. All concepts discussed in lecture will be
implemented in VHDL.
| Date | Topic | Slides/Reading Material |
|---|---|---|
| W, January 6 | Course Intro |
Slides |
| F, January 8 | VHDL Intro (guidelines, entity and architecture, basic mux implementation) | Tutorial |
| M, January 11 | VHDL Intro (if vs. case, priority encoder, structural architectures) |
Tutorial (read combinational logic and structural description sections)
4x1 mux used in class See Ch. 6 for priority encoder example. |
| W, January 13 |
Lab 1 Structural Architectures, Cont. | |
| F, January 15 | Arithmetic Operations, Testbenches |
Add w/ carry examples in different packages: numeric_std std_logic_arith with std_logic_unsigned std_logic_arith Common Problems: Signal/variable comparison |
| M, January 18 | Holiday | |
| W, January 20 | Lab 2, Generics, Avoiding Latches, Testbenches | |
| F, January 22 | Carry-Lookahead Adders | Read Section 5.4 |
| M, January 25 | Lab 3, For-generate | |
| W, January 27 | Misc. VHDL (initialization of signals, generics, configurations) | |
| F, January 29 | Advanced testbench techniques Sequential logic (see tutorial examples) |
|
| M, February 1 | Synthesis of Sequential logic (see tutorial examples) | |
| W, February 3 | No class | |
| F, February 5 | Midterm 1 Review | |
| M, Feb 8 | Finite State Machines | See tutorial. Direct link. |
| W, Feb 10 | Lab 4 | See counter example in sequential logic section of the tutorial. |
| F, Feb 12 | Midterm 1 | |
| M, February 15 | FSMD |
See Controllers+Datapath section of VHDL tutorial. Fibonacci Calculator FSMD (1-process model) Fibonacci code and datapath |
W, Feb 17 | FSM+D, Lab 5 | F, Feb 19 | Midterm 1 Discussion, Lab 5 | M, Feb 22 | Lab 6 | W, Feb 24 | Lab 6, Cont. | F, Feb 26 | Chisel (References to be added) | M, Mar 7 | Arrays, If Generate (see delay example on tutorial) |
| W, March 9 | FPGA Architectures |
FPGA Architecture Slides
Cyclone II Datasheet Cyclone II Figures Cyclone II Family Overview Cyclone III Family Handbook Cyclone III Family Overview |
| F, March 11 | FPGA Architectures, Cont. | |
| M, March 14 | FPGA Architectures, Cont. | |
| W, March 16 | Midterm 2 Review | |
| F, March 18 | Midterm 2 | |
| M, March 21 | Small 8 Intro, Buses, Tristates | Bus/Tristate Code |
| W, March 23 |
Midterm 2 Discussion Small 8 ALU, Internal Architecture, Ports |
|
| F, March 25 | Small 8 Instruciton Set | |
| M, March 28 | Small 8 Instruction Set | |
| W, March 30 | Small 8 Instruction Set | |
| F, April 1 | Small 8 Instruction Set | |
| M, April 4 | Class Cancelled | |
| W, April 6 |
Small 8 MIF files and Assembly Code 2-process FSMD |
2-process FSMD code |
| F, April 8 | Metastability, Clock-Domain Crossing | Papers |
| M, April 11 | Metastability, Clock-Domain Crossing, Cont. | |
| W, April 13 |
Pareto Optimality Design-space exploration |