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Parent Directory | - | ||
guest/ | 2019-01-05 17:56 | - | |
metastability/ | 2019-01-05 17:56 | - | |
276202.pdf | 2018-08-16 12:27 | 77K | |
6544743.pdf | 2018-08-16 12:27 | 182K | |
CAW16_F1-17.pptx | 2018-08-16 12:28 | 1.9M | |
Catapult_UFlorida_2014_Putnam.pptx | 2018-08-16 12:28 | 18M | |
EEIOL_2007DEC24_EDA_TA_01.pdf | 2018-08-16 12:27 | 405K | |
F2-Overview.ppt | 2018-08-16 12:27 | 3.3M | |
F2.ppt | 2018-08-16 12:27 | 2.8M | |
F3_Nov26_RC.ppt | 2018-08-16 12:27 | 3.7M | |
F4.ppt | 2018-08-16 12:27 | 1.2M | |
F209.ppt | 2018-08-16 12:27 | 3.9M | |
ImpulseC.ppt | 2018-08-16 12:27 | 1.0M | |
NallatechLectureSlides.pdf | 2018-08-16 12:28 | 292K | |
Novo-G.ppt | 2018-08-16 12:27 | 7.4M | |
RC-2014-12-10.pptx | 2018-08-16 12:28 | 2.1M | |
RCML_Lecture.ppt | 2018-08-16 12:27 | 1.1M | |
RC_08_F1.ppt | 2018-08-16 12:27 | 1.8M | |
RC_Class_F4.pptx | 2018-08-16 12:27 | 9.1M | |
RC_Class_F5_2008.pdf | 2018-08-16 12:27 | 2.7M | |
SCL framework_RC_class.ppt | 2018-08-16 12:27 | 5.0M | |
SHMEM_hprcta_pdf.pdf | 2018-08-16 12:27 | 2.1M | |
SystemVerilog and Verification Slides.pptx | 2018-12-03 08:50 | 6.5M | |
buffers_1.1.ppt | 2018-08-16 12:28 | 204K | |
buffers_1.2.ppt | 2018-08-16 12:27 | 397K | |
buffers_1.3.ppt | 2018-08-16 12:27 | 1.4M | |
cdc_wp.pdf | 2018-08-16 12:27 | 367K | |
device_tradeoffs.ppt | 2018-09-10 09:31 | 475K | |
elastic.pptx | 2018-08-16 12:27 | 349K | |
fsmd_examples.zip | 2018-08-16 12:27 | 5.6K | |
highlevelsynth_1.5.ppt | 2018-08-16 12:28 | 1.8M | |
highlevelsynth_1.6.ppt | 2018-08-16 12:27 | 2.0M | |
highlevelsynth_1.7.ppt | 2018-08-16 12:27 | 2.0M | |
highlevelsynth_1.8.ppt | 2018-08-16 12:27 | 2.0M | |
highlevelsynth_1.9.ppt | 2018-08-16 12:27 | 2.0M | |
hwsw_1.2.ppt | 2018-08-16 12:27 | 252K | |
if.pdf | 2018-08-16 12:27 | 2.8M | |
if.pptx | 2018-08-16 12:27 | 1.0M | |
intro.ppt | 2018-08-16 12:28 | 2.0M | |
lecture1.ppt | 2018-08-21 21:36 | 1.2M | |
opt_prob.ppt | 2018-08-16 12:28 | 248K | |
opt_prob_1.1.ppt | 2018-08-16 12:27 | 249K | |
opt_prob_1.2.ppt | 2018-08-16 12:28 | 234K | |
overlays_msr_2015.pptx | 2018-08-16 12:28 | 2.6M | |
parallel_circuits.ppt | 2018-08-16 12:27 | 1.0M | |
parallel_circuits_1_1.ppt | 2018-08-16 12:27 | 788K | |
parallel_circuits_1_2.ppt | 2018-08-16 12:28 | 702K | |
partial_reconfig.ppt | 2018-08-16 12:27 | 856K | |
pr_intro_4-11-08.ppt | 2018-08-16 12:27 | 781K | |
rc_architecture_1.0.ppt | 2018-08-16 12:28 | 205K | |
rc_architecture_1.4.ppt | 2018-08-16 12:28 | 562K | |
rc_architecture_1.5.ppt | 2018-08-16 12:28 | 663K | |
rc_architecture_1.6.ppt | 2018-08-16 12:27 | 1.8M | |
rc_architecture_1.7.ppt | 2018-08-16 12:27 | 1.8M | |
rc_architecture_1.10.ppt | 2018-08-16 12:27 | 1.8M | |
rc_architecture_1.11.ppt | 2018-08-16 12:28 | 4.6M | |
rc_architecture_1.12.ppt | 2018-08-16 12:28 | 4.7M | |
rc_architecture_1.13.ppt | 2018-08-16 12:28 | 4.7M | |
rc_architecture_1.14.ppt | 2018-09-12 08:24 | 4.7M | |
rt_synth.ppt | 2018-08-16 12:28 | 393K | |
rt_synth_1.1.ppt | 2018-08-16 12:28 | 596K | |
rt_synth_1.2.ppt | 2018-08-16 12:27 | 595K | |
rt_synth_1.3.ppt | 2018-09-26 08:30 | 660K | |
shaw2014_opencl.pptx | 2018-08-16 12:28 | 3.5M | |
systolic_1.3.ppt | 2018-08-16 12:28 | 689K | |
systolic_1.4.ppt | 2018-08-16 12:28 | 967K | |
warp.ppt | 2018-08-16 12:27 | 1.9M | |