Fundamental concepts at advanced undergraduate level (EEL4720) and introductory graduate level (EEL5721) in reconfigurable computing based upon advanced technologies in field-programmable logic devices. Topics include general concepts, device architectures, design tools, metrics and kernels, system architectures, and application case studies.
| Date | Topic | Slides/Reading Material |
|---|---|---|
| W, Aug 22 | Course info, Intro to RC |
Slides Overview Paper: Compton, Hauck Survey Motivating FPGA Example: Scalable Window Generation for the Intel Broadwell+Arria 10 and High-Bandwidth FPGA Systems Tutorial: Start reading "My VHDL Tutorial" under VHDL Resources. |
| F, Aug 24 | VHDL Tutorial (Combinational Logic) | See combinational logic section of "My VHDL Tutorial" under VHDL Resources. |
| M, Aug 27 | VHDL Tutorial (Combinational Logic, Cont.) | See my tutorial. |
| W, Aug 29 | VHDL Tutorial (Sequential Logic) | See my tutorial. |
| F, Aug 31 | VHDL Tutorial (Sequential Logic, Cont., Structural Architectures) | See my tutorial. |
| M, Sep 3 | Holiday | |
| W, Sep 5 | VHDL Tutorial (Finite-State Machines, FSMD, FSM+D) |
See finite state machine section and controller+datapath section of tutorial. Additional FSMD example used in class |
| F, Sep 7 | VHDL Tutorial (FSMD, FSM+D, Testbenches) | |
| M, Sep 10 | VHDL Tutorial (FSM+D, Cont.) Device Tradeoffs |
Slides Measuring the Gap between FPGAs and ASICs |
W, Sep 12 | Device Tradeoffs, Cont. FPGA Architectures |
Architecture Slides | F, Sep 14 | FPGA Architectures, Cont. | M, Sep 17 | FPGA Architectures, Cont. | W, Sep 19 | Lab 2 | F, Sep 21 | Lab 2, Cont. Misc. VHDL |
| M, Sep 24 | Optimization Problems | Slides |
| W, Sep 26 |
Optimization Problems, Cont. RT Synthesis, Placement, and Routing |
Slides
Papers: Placement/Routing, Pathfinder, Versatile Place+Route (VPR) |
| F, Sep 28 |
RT Synthesis, Placement, and Routing, Cont. Pipelining, Parallelism, Systolic Arrays |
Pipelining Slides |
| M, Oct 1 | Pipelining, Cont. | |
| W, Oct 3 | Lab 3 | |
| F, Oct 5 | Midterm 1 Review | |
| M, Oct 8 | Midterm 1 | |
| W, Oct 10 | Pipelining, Cont. | |
| F, Oct 12 |
VHDL: for-generate, if-generate, delay example Lab 4 |
|
| M, Oct 15 |
Lab 4, Cont. High-Level Synthesis |
High-level Synthesis Slides |
| W, Oct 17 | High-Level Synthesis, Cont. | |
| F, Oct 19 | High-Level Synthesis, Cont. | |
| M, Oct 22 | High-Level Synthesis, Cont. | |
| W, Oct 24 |
Midterm 1 Solution Discussion High-Level Synthesis, Cont. |
|
| F, Oct 26 |
High-level Synthesis Metastability, Clock-Domain Crossing |
Papers Basics of setup and hold time |
| M, Oct 29 | Metastability, Clock-Domain Crossing, Cont. | |
| W, Oct 31 | Lab 5 | |
| F, Nov 2 | No class (homecoming) | |
| M, Nov 5 | Buffering |
Buffering Slides
Paper 1 Paper 2 Sliding-Window Paper Sliding-Window Paper on Broadwell+Arria10 |
| W, Nov 7 |
Buffering, Cont Final Project |
|
| F, Nov 9 | Class Cancelled (see email for signal-buffer lecture) | |
| W, Nov 14 | Final Project (DMA Read Interface for DRAM) | |
| F, Nov 16 |
Final Project (DMA Write Interface for DRAM, Padding, Testbenches) |
|
| M, Nov 19 |
Final Project (Misc. Issues) |
|
| M, Nov 26 |
2-process FSMD Hw/Sw Partitioning |
2-process FSMD code Slides System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search An Evaluation of Bipartitioning Techniques |
| W, Nov 28 |
Absorption FIFOs Overlays |
Papers: High-Frequency Absorption-FIFO Pipelining for Stratix 10 HyperFlex Intermediate Fabrics Fast, Flexible High-Level Synthesis form OpenCL using Reconfiguration Contexts Adjustable-Cost Overlays for Runtime Compilation |
| F, Nov 30 | Midterm 2 Review | |
| M, Dec 3 | SystemVerilog Verification | Slides |