EEL4720/5721 - Reconfigurable Computing (Fall 2014)


The late penalty for all assignments is 10% per day. Anything more than 5 minutes late is one day late.

Midterm 1 has changed to Wed, Oct 15.

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Fundamental concepts at advanced undergraduate level (EEL4720) and introductory graduate level (EEL5721) in reconfigurable computing based upon advanced technologies in field-programmable logic devices. Topics include general concepts, device architectures, design tools, metrics and kernels, system architectures, and application case studies.

Course Information


Date Topic Slides/Reading Material
M, Aug 25 Course info, Intro to RC Slides
Paper: Compton, Hauck Survey
Tutorials: Start reading "My Tutorial" under VHDL Resources.
W, Aug 27 VHDL Tutorial (Combinational Logic) See combinational logic section of "My Tutorial" under VHDL Resources.
F, Aug 29 VHDL Tutorial (Combinational Logic) See my tutorial.
W, Sep 3 VHDL Tutorial (Combinational Logic, Sequential Logic) See my tutorial.
F, Sep 5 VHDL Tutorial (Sequential Logic, Structural Architectures) See my tutorial.
M, Sep 8 VHDL Tutorial (Finite State Machines, FSMDs, FSM+Ds) See my tutorial.
Additional FSMD example used in class
W, Sep 10 VHDL Tutorial (FSMDs)
Device Tradeoffs
F, Sep 12 Device Tradeoffs, Cont.
M, Sep 15 Testbench Overview
FPGA Architectures
GCD Code and Testbench from Class
Architecture Slides
W, Sep 17 FPGA Architectures, Cont.
F, Sep 19 Class cancelled
M, Sep 22 FPGA Architectures, Cont.
W, Sep 24 Lab 2 Discussion
Reconfigurable Architectures, Cont.
Nallatech Board Slides
F, Sep 26 Reconfigurable Architectures, Cont.
M, Sep 29 Reconfigurable Architectures, Cont.
Optimization Problems
W, Oct 1 Lab 3
F, Oct 3 RT Synthesis, Placement, and Routing Slides
Papers: Placement/Routing, Pathfinder, Versatile Place+Route (VPR)
M, Oct 6 RT Synthesis, Placement, and Routing, Cont.
Pipelining, Parallelism, Systolic Arrays
Pipelining Slides
W, Oct 8 Pipelining, Parallelism, Systolic Arrays, Cont.
F, Oct 10 Pipelining, Parallelism, Systolic Arrays, Cont.
M, Oct 13 Midterm 1 Review
W, Oct 15 Midterm 1
F, Oct 17 No class
M, Oct 20 Pipelining, Parallelism, Systolic Arrays, Cont.
Lab 4
W, Oct 22 Midterm 1 Discussion
Metastability, Clock-Domain Crossing
F, Oct 24 Class Cancelled
M, Oct 27 Metastability, Cont.
W, Oct 29 Metastability, Cont.
Lab 5
High-level Synthesis
High-level Synthesis Slides
F, Oct 31 High-level Synthesis, Cont.
M, Nov 3 High-level Synthesis, Cont.
W, Nov 5 High-level Synthesis, Cont.
F, Nov 7 High-level Synthesis, Cont.
M, Nov 10 High-level Synthesis, Cont.
Final Project
W, Nov 12 Final Project
F, Nov 14 Final Project
Buffering Slides
Paper 1
Paper 2
Sliding-Window Paper
M, Nov 17 Buffering, Cont.
W, Nov 19 Buffering, Cont.
F, Nov 21 Final Project
M, Nov 24 Hardware/software partitioning Hw/Sw Partitioning Slides
System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search
An Evaluation of Bipartitioning Techniques
W, Nov 26 No class (holiday)
F, Nov 28 No class (holiday)
M, Dec 1 Hardware/software partitioning, cont.
Midterm 2 Review
W, Dec 3 No Class
F, Dec 5 Midterm 2
M, Dec 8 Catapult
OpenCL High-level Synthesis, Fast Compilation
Catapult Slides
W, Dec 10 Reconfigurable computing in space Slides

VHDL Resources