The final project is due on Friday, Decemeber 6. The second midterm will either be on Monday, December 2 or Wednesday, December 4.
Midterm 1 is on Oct 9 in class and Oct 8-10 for EDGE students. Closed note, close book.
Lab 1 extend to Friday Sep 13 to help people just starting with VHDL.
Fundamental concepts at advanced undergraduate level (EEL4720) and introductory graduate level (EEL5721) in reconfigurable computing based upon advanced technologies in field-programmable logic devices. Topics include general concepts, device architectures, design tools, metrics and kernels, system architectures, and application case studies.
|W, Aug 21||Course info, Intro to RC||
Paper: Compton, Hauck Survey
Tutorials: Start reading "My Tutorial" under VHDL Resources.
|F, Aug 23||VHDL Tutorial (Combinational Logic)||See combinational logic section of "My Tutorial" under VHDL Resources.|
|M, Aug 26||VHDL Tutorial (Combinational Logic, Cont.)||See tutorial.|
|W, Aug 28||VHDL Tutorial (Sequential Logic, Structural Architectures)||See tutorial.|
|F, Aug 30||VHDL Tutorial (Finite State Machines, FSMDs)||See tutorial.|
|W, Sep 4||VHDL Tutorial (FSM+Ds, FSMDs, Testbenches)||
Example used in class.
Code from class
|F, Sep 6||VHDL Tutorial (Testbenches)
Testbench from class.
|M, Sep 9||Device Tradeoffs, Cont.
|W, Sep 11||Reconfigurable Architectures, Cont.|
|F, Sep 13||
Lab 2 Discussion
Reconfigurable Architectures, Cont.
|Nallatech Board Slides|
|M, Sep 16||Reconfigurable Architectures, Cont.|
|W, Sep 18||Optimization Problems||Slides|
|F, Sep 20||RT Synthesis, Placement, and Routing||
Papers: Placement/Routing, Pathfinder, Versatile Place+Route (VPR)
|M, Sep 23||Class cancelled|
|W, Sep 25||Lab 3 Discussion|
|F, Sep 27||Placement and Routing, Cont.|
|M, Sep 30||Pipelining, Parallelism, Systolic Arrays||
|W, Oct 2||Pipelining, Parallelism, Systolic Arrays, Cont.||
|F, Oct 4||Midterm review||
|M, Oct 7||Pipeline, Cont.
Lab 4 Discussion
|W, Oct 9||Midterm 1||
|F, Oct 11||Midterm Discussion, Lab 4 Discussion||
|M, Oct 14||Metastability, Clock-Domain Crossing||Papers|
|W, Oct 16||Class Cancelled|
|F, Oct 18||Metastability, Clock-Domain Crossing, Cont.
Lab 5 Discussion
|M, Oct 21||Final Project Discussion
Misc VHDL Topics (arrays, generate, integers)
|W, Oct 23||Misc VHDL Topics (arrays, generate, integers)
|F, Oct 25||Buffering, Cont.|
|M, Oct 28||Final Project|
|W, Oct 30||Final Project, Cont.|
|F, Nov 1||High-level Synthesis||Slides|
|M, Nov 4||High-level Synthesis, Cont.|
|W, Nov 6||High-level Synthesis, Cont.|
|W, Nov 13||High-level Synthesis, Cont.|
|F, Nov 15||High-level Synthesis, Cont.|
|M, Nov 18||Intermediate Fabrics||Video for lecture|
|W, Nov 20||High-level Synthesis, Cont.
Hw/Sw Partitioning Slides
System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search
An Evaluation of Bipartitioning Techniques