The objectives of this course are to learn, understand, and extend existing design techniques for FPGAs and other reconfigurable devices. Specific goals include gaining experience with advanced pipelining strategies, techniques for creating scalable, high-frequency pipelines, experience with FPGA virtualization strategies and high-level synthesis tools, while also evaluating FPGA application studies in embedded and high-performance domains.
| Date | Topic | Slides/Reading Material |
|---|---|---|
| M, Jan 13 | Course info, Intro |
Slides Start reading my SystemVerilog tutorial. |
| W, Jan 15 | SystemVerilog: Combinational Logic (Basic constructs, 2x1 mux) |
Github repo for combinational logic 2x1 mux code Design the circuit, then write the code (optional) |
| F, Jan 17 | SystemVerilog: Combinational Logic (Basic constructs, 4-input priority encoder) |
4-input priority encoder Article explaining "unique" keyword |
| W, Jan 22 | SystemVerilog: Combinational Logic (Parameterized priority encoder, adder) |
Parameterized priority encoder Adder code |
| F, Jan 24 |
SystemVerilog: Combinational Logic, Cont. (Mult, ALU) |
Multiplier code ALU code |
| M, Jan 27 |
SystemVerilog: Structural Architectures (4x1 mux, ripple-carry adder, delay) |
Github repo for structural architectures You Can (and Should) Write Recursive RTL Code You Can (and Should) Write Recursive RTL: Part 2 |
| W, Jan 29 |
SystemVerilog: Sequential Logic |
Github repo for sequential logic Blocking vs. Non-blocking assignments Crafting Clean Reset Logic Sequential logic example Schematic of architectures |
| F, Jan 31 |
SystemVerilog: Sequential Logic, Cont. |
|
| M, Feb 3 |
SystemVerilog: Sequential Logic, Cont. SystemVerilog: Finite State Machines |
Github repo for FSMs FSM Design & Synthesis using SystemVerilog |
| W, Feb 5 |
Lab 1 (See Canvas) SystemVerilog: Finite State Machines, Cont. |
|
| F, Feb 7 |
SystemVerilog: Finite State Machines, Cont. |
|
| M, Feb 10 | SystemVerilog: Finite State Machines and Datapaths (FSMDs) | Github repo for FSMs + Datapaths |
| W, Feb 12 | SystemVerilog: Finite State Machines and Datapaths, Cont. (FSM+Ds) | |
| F, Feb 14 |
SystemVerilog: Finite State Machines and Datapaths, Cont. (FSM+Ds) Design-space exploration for throughput, latency, and area |
|
| M, Feb 17 |
SV testbenches: basic examples |
Github repo for SV testbenches (see basics section) |
| W, Feb 19 |
SV testbenches: race conditions SV "gotchas" |
Race Conditions: The Root of All Verilog Evil SystemVerilog Event Regions, Race Avoidance & Guidelines Race condition examples Github repo for SV "gotchas" |
| F, Feb 21 |
Lab 2 SV testbenches: race conditions, cont. SV testbenches: basics, cont. |
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| M, Feb 24 |
SV testbenches: race conditions, cont. SV testbenches: basics, cont. |
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| W, Feb 26 |
SV testbenches: basics, cont. SV testbenches: assertions, sequences, implication |
Github repo for assertions (see assertions section) Doulos assertions tutorial |
| F, Feb 28 | SV testbenches: assertions, sequences, implication, cont. |
Github repo for assertions (see assertions section) |
| M, Mar 3 | Midterm Review | |
| W, Mar 5 | SV testbenches: assertions, sequences, implication, cont. | |
| F, Mar 7 | Midterm | |
| M, Mar 10 | SV testbenches: assertions, sequences, implication, cont. | |
| W, Mar 12 | SV testbenches: assertions, cont. | |
| F, Mar 14 | SV testbenches: coverage, cover properties, cover groups/points |
Github repo (see coverage and CRV section) |
| M, Mar 24 | SV testbenches: constrained-random verification | |
| W, Mar 26 | SV testbenches: Universal Verification Methodology (UVM) intro (basics) |
Intro example |
| F, Mar 28 | SV testbenches: Universal Verification Methodology (UVM) intro (agents) |
Agent and coverage example |
| M, Mar 31 | SV testbenches: Universal Verification Methodology (UVM) intro (tests, sequences, environments) |
Example |
| W, April 2 |
SV testbenches: Universal Verification Methodology (UVM), cont. Lab 4 |
Example 1 Example 2 |
| F, April 4 |
Lab 4, Cont. Timing Optimization: background, common strategies |
Background video Github repo for timing optimization (includes slides) |
| M, April 7 | Timing Optimization: common strategies | Timing optimization strategies video |
| W, April 9 | Timing Optimization: Quartus timing analyzer overview, add tree example |
Timing analyzer overview Add tree example |
| F, April 11 | Timing Optimization: timer examples, reset reduction |
Timer example 1 Timer example 2 Reset reduction example |
| M, April 14 | Timing Optimization: multi-cycle paths, counter |
Multi-cycle paths Counter FSM(D) tips slides |
| W, April 16 | Timing Optimization: register duplication, reset tree, 3-input adder |
Register duplication example Reset tree example 3-input adder |
| F, April 18 | Timing Optimization: add/sub, RAMs |
Add/sub example |
| M, April 21 | Timing Optimization: RAMs, cont. | |
| W, April 23 |
Timing Optimization: FIFOs Misc UVM |