Announcements

• The midterm is on Friday, March 6
• The final is on Thursday, April 30 (730am to 930am)
• The late penalty for all assignments is 10% per day. Anything more than 5 minutes late is one day late.

Overview

The objectives of this course are to learn, understand, and extend existing design techniques for FPGAs and other reconfigurable devices. Specific goals include gaining experience with advanced pipelining strategies, techniques for creating scalable, high-frequency pipelines, experience with FPGA virtualization strategies and high-level synthesis tools, while also evaluating FPGA application studies in embedded and high-performance domains.

Course Information

• Syllabus
• Canvas
• Professor
  Dr. Greg Stitt (gstitt@ece.ufl.edu), Office Hours (M Period 3) by appointment (all office hours on Zoom, see Canvas link)
  
• TA/Supervised Teacher
  • Wes Piard (wespiard@ufl.edu), Office Hours (by appointment)
• Lecture
  M W F, Period 2 (8:30-9:20 AM), Online

Lectures

SystemVerilog Resources

• My SystemVerilog tutorial
• My timing optimization tutorial
• 2017 SystemVerilog Standard
• 2012 SystemVerilog Standard
• ChipVerify SystemVerilog tutorials
• Doulos SystemVerilog tutorials
• Synthesizing SystemVerilog
• SystemVerilog "Gotchas"
• Blocking vs. Non-blocking assignments
• SV port defaults
• SV defaults
• SystemVerilog.io Tutorials
• SV data types
• SV data types and objects
• Verilog Pro SV posts
• SystemVerilog-2009 Enhancements: Priority/Unique/Unique0
• SV cheat sheet
• SV Race Conditions
• Tricky SVA Poperties Made Easy
• VHDL, Verilog, Modelsim Tutorials
• Numerous Verilog Tips (many apply to VHDL)
• Tradeoffs between synchronous and asynchronous resets
• Asynchronous & Synchronous Reset Design Techniques
• Reset Bridge
• Excellent article on false paths and multi-cycle paths