-- Greg Stitt -- University of Florida library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity add_tb is end add_tb; architecture TB of add_tb is component add port ( in1 : in std_logic_vector(7 downto 0); in2 : in std_logic_vector(7 downto 0); sum : out std_logic_vector(7 downto 0); carry : out std_logic); end component; signal in1 : std_logic_vector(7 downto 0); signal in2 : std_logic_vector(7 downto 0); signal sum_bad : std_logic_vector(7 downto 0); signal sum_good1 : std_logic_vector(7 downto 0); signal sum_good2 : std_logic_vector(7 downto 0); signal sum_good3 : std_logic_vector(7 downto 0); signal carry_bad : std_logic; signal carry_good1 : std_logic; signal carry_good2 : std_logic; signal carry_good3 : std_logic; begin -- TB U_BAD : entity work.add(BAD) port map ( in1 => in1, in2 => in2, sum => sum_bad, carry => carry_bad); U_GOOD1 : entity work.add(GOOD1) port map ( in1 => in1, in2 => in2, sum => sum_good1, carry => carry_good1); U_GOOD2 : entity work.add(GOOD2) port map ( in1 => in1, in2 => in2, sum => sum_good2, carry => carry_good2); U_GOOD3 : entity work.add(GOOD3) port map ( in1 => in1, in2 => in2, sum => sum_good3, carry => carry_good3); process begin -- test all input combinations for i in 0 to 255 loop for j in 0 to 255 loop in1 <= std_logic_vector(to_unsigned(i,8)); in2 <= std_logic_vector(to_unsigned(j,8)); wait for 10 ns; end loop; -- j end loop; -- i wait; end process; end TB;