We will also be using the Digilent Analog Discovery Board. If you have not purchased it yet, you can here: http://www.digilentinc.com/Products/Detail.cfm?Prod=ANALOG-DISCOVERY

Lab workarounds

• If you are using Quartus 9.1 and get an error about incremental compilation when using Signal Tap, do the following: add "set_global_assignment -name INCREMENTAL_COMPILATION OFF" to the .qsf file in the project folder. If incremental compilation is turned off and you get a license file error, it's likely because you added post-fit nodes instead of pre-synthesis nodes in Signal Tap.

Lab 0: (Week 2: Jan 9-13)

1. Obtain and test board in lab. If you have questions about the board, you can read the manual here.
2. Install free web edition of Quartus: Link. You don't actually need the latest version if you already have a version installed that supports the required FPGA. Quartus 13.1 is the last version that supports the FPGA we are using. Before downloading, make sure the ModelSim option is selected. You can unselect device support for everything except the Cyclone III if you need to save disk space.
3. Read over the following tutorials (ignore references to lab assignment tasks. You will be using these tools as part of the next lab)
   • Oscillosope Tutorial
   • Signal Tap Tutorial (ignore line ment ioning "Incremental Build")
   • Digilent Analog Discovery Getting Started
4. Review Quartus Tutorials 1 and 3 (Appendices in textbook)
5. Start reading the ModelSim tutorial. You do not need to finish the entire tutorial, but you will be using this tool all semester, so make sure you understand the basics. You can install a free version of Modelsim from the earlier Quartus link. Or, if you already have Quartus installed, open my earlier link. Next to the Quartus II Web Edition column is a ModelSim-Altera column. You want to select the ModelSim-Altera Starter Edition link. I'm not sure if it has to match your version of Quartus, but I would recommend installing the version that is listed next to your version of Quartus.

Lab 1: Introduction to EEL 4712 Digital Design Lab (Week 3: Jan 17-23)

• Lab Instructions
• VHDL Files
  
  
• Checklist

Lab 2: Generic-Width Behavioral ALU (Week 4: Jan 24-Jan 30)

• Lab Instructions
• Small sample testbench for alu_ns
• Top level entity

You will find these incredibly useful:

• VHDL Package Reference
• VHDL Math Tricks (Comparison of std_logic_arith and numeric_std)

• Lab 2 Checklist

Lab 3: Ripple-Carry and Carry-Lookahead Adders (Week 5: Jan31-Feb6)

• Lab Instructions
• Adder entity skeleton code
• Provided testbench
• Top-level entity

• Top-level for timing simulation
• Testench for timing simulation

• Lab 3 Checklist

Lab 4: Finite State Machines (Week 7: Feb14-Feb20)

• Lab Instructions
• All provided code

• Lab 4 Checklist

Lab 5: GCD Calculator (Week 8: Feb21-Feb27)

• Lab Instructions
• All provided code
• For additional extra credit, please test the vJTAG interface that enables communication between your laptop and DE0 board. First, download extra_credit.zip. Read the instructions in GUI_Instructions.doc. Add your lab5 gcd code to the specified project. As part of the pre-lab submission, create a separate report that specifies the operating system version you are using, and any problems you encountered. Future labs will use a polished version of this interface, so I'm looking for any suggestions you might have.

• Lab 5 Checklist

Lab 6: VGA Interfacing (Week 9-10: Feb28-March20) The second week is optional for those that finish early. Everyone must attend the first week.

• Lab Instructions
• MIF file instructions
• All provided code

• Lab 6 Checklist

Final Project: MIPS-like Microprocessor (3 weeks, Starts on Tuesday, March 28)

• Instructions (SUBJECT TO CHANGE)
• All provided material