Midterm 3 is scheduled for the last day of classes, Wednesday, April 25.
Midterm 2 is tentatively scheduled for Friday, March 23.
Class is cancelled on Wed, Feb 22 and Fri, Feb 24. Please use the opportunity to work ahead on labs.
Midterm 1 will be on Friday, February 17 during the normal lecture.
Labs start Monday, January 9th. Please read Lab 0 now! You should already know exactly what to do before you get to lab.
Advanced modular logic, design languages, finite state machines and binary logic.
This course will review basic concepts in digital logic (muxes, decoders,
encoders, etc.) and will build upon these concepts to form complex digital
circuits consisting of finite state machines, controllers, and datapaths. The
course will be lab intensive and will provide realistic case studies to apply
concepts learned during lecture. All concepts discussed in lecture will be
implemented in VHDL.
|M, January 9||Course info, Intro||
|W, January 11||VHDL Intro (guidlines, entity and architecture, basic mux implementation)||Tutorial|
|F, January 13||VHDL Intro Cont. (combinational logic, behavioral and structural architectures)||
Tutorial (read combinational logic and structural description sections)
4x1 mux used in class
|W, January 18||Lab 1 Discussion (see lab page)|
|F, January 20||Arithmetic Operations in std_logic_arith and numeric_std||
Add w/ carry examples in different packages:
std_logic_arith with std_logic_unsigned
|M, January 23||Arithmetic Operations, Cont.
|See VHDL tutorial.|
|W, January 25||Arithmetic Operations, Cont.
|See VHDL tutorial. Class code provided by email.|
|F, January 27||Lab 2, Cont.
|See VHDL tutorial (structural ripple-carry example).|
|M, January 30||Carry lookahead adders
||Read section 5.4|
|W, Feb 1||Lab 3
||See lab page|
|F, Feb 3||Sequential Logic
||See VHDL tutorial|
|M, Feb 6||Sequential Logic, State machines
||See VHDL tutorial|
|W, Feb 8||Lab 4||See lab page.|
|F, Feb 10||Lab 4, Cont., Finite-State Machines w/ Datapaths (FSMDs)||
Fibonacci Calculator FSMD (1-process model)
See VHDL tutorial for more examples.
|M, Feb 13||Midterm 1 Review|
|W, Feb 15||FSMDs cont.||See previous Fibonacci example and FSMD section of tutorial.|
|F, Feb 17||Midterm 1|
|M, Feb 20||FSM+D, Lab 5||See the Controllers+Datapaths section of the tutorial and lab5 page.|
|W, Feb 22||No class|
|F, Feb 24||No class|
|M, Feb 27||Arrays, if generate, misc topics||See delay entity example in VHDL tutorial.|
|W, Feb 29||Arrays, if generate, misc topics, cont.
|F, Mar 2||Lab 6, cont.|
|M, Mar 12||FPGA Architectures||
FPGA Architecture Slides
Cyclone II Datasheet
Cyclone II Figures
Cyclone II Family Overview
|W, Mar 14||FPGA Architectures, Cont.|
|F, Mar 16||
FPGA Architectures, Cont.
Altera Guidelines for Memories (pg.12-35)
Xilinx Guidelines for Memories (pg.144-195)
|M, Mar 19||Midterm 2 Review|
|W, Mar 21||
Small 8 Intro, Buses, Tristates
2-process FSMD code
|F, Mar 23||Midterm 2|
|M, Mar 26||Small 8, Cont.|
|W, Mar 28||Small 8, Cont.|
|F, Mar 30||Small 8, Cont.|
|M, April 2||No class|
|W, April 4||Small 8, Cont.|
|F, April 6||Small 8, Cont.|
|M, April 9||Metastability, Clock-Domain Crossing||Related papers|
|W, April 11||Metastability, Clock-Domain Crossing, Cont.|
|F, April 13||Design-space exploration, Pareto-optimal implementations|
|M, April 16||
Design-space exploration, Pareto-optimal implementations, Cont.
Loop Unrolling, Pipelining
|W, April 18||FPGA, GPU, multi-core comparison for sliding-window applications||
|F, April 20||Midterm 3 Review|
|M, April 23||Research Overview||
Summary of FPGA Limitations