Midterm 3 will be on Wednesday, April 20th during lecture.
Midterm 2 will be on Friday, March 18 during lecture.
Midterm 1 will be on Friday, February 11 during lecture.
The final grade for the class will be based on 3 midterms (20% each) in addition to labs (40%). Don't be confused by the syllabus or slides, which I haven't updated yet.
Labs start Monday, January 10th. Please read Lab 0 now! You should already know exactly what to do before you get to lab.
Advanced modular logic, design languages, finite state machines and binary logic.
This course will review basic concepts in digital logic (muxes, decoders,
encoders, etc.) and will build upon these concepts to form complex digital
circuits consisting of finite state machines, controllers, and datapaths. The
course will be lab intensive and will provide realistic case studies to apply
concepts learned during lecture. All concepts discussed in lecture will be
implemented in VHDL.
|W, January 5||Course info, Intro||
|F, January 7||VHDL Intro||
Read chapter 6
|M, January 10||VHDL, Combinational Logic|
|W, January 12||Lab 1 Discussion||See lab page.|
|F, January 14||Arithmetic Operations in std_logic_arith and numeric_std||
Add w/ carry examples in different packages:
std_logic_arith with std_logic_unsigned
|W, January 19||Arithmetic Operations, Cont.
|See VHDL tutorial.|
|F, January 21||Testbenches, Cont.
|See VHDL tutorial.|
|M, January 24||Case study: Carry-lookahead adder||
Read section 5.4
|W, January 26||Lab 3 Discussion||
Read about generate statements (see index)
|F, January 28||Sequential Logic||
|M, Jan 31||Finite State Machines||
|W, Feb 2||Finite State Machines (2-process model)||
|F, Feb 4||Finite State Machines with Integrated Datapaths (FSMD)||
Fibonacci Calculator FSMD (1-process model)
Also, see example in my tutorial, which is more detailed.
|M, Feb 7||Finite State Machines with Integrated Datapaths (FSMD), Cont.|
|W, Feb 9||Midterm 1 Review|
|F, Feb 11||Midterm 1|
|M, Feb 14||Finite State Machines + Explicit Datapaths (FSM+D)||
Fibonacci Calculator FSM+D
fib, datapath, and ctrl are the most important entities. Make sure to compare this with the FSMD model posted earlier.
Also, compare FSMD and FSM+D for the bit difference calculator from the tutorial.
|W, Feb 16||Lab 5
Arrays, packages, functions
|Read over delay example in tutorial.|
|F, Feb 18||Arrays, Memories||
Altera Guidelines for Memories (pg.12-35)
Xilinx Guidelines for Memories (pg.144-195)
Read sum example in tutorial.
|M, Feb 21||VGA Interface||Read lab 6 instructions.|
|W, Feb 23||VGA Interface, Cont.
FPGA Architecture Slides
Cyclone II Datasheet
Cyclone II Figures
Cyclone II Family Overview
|F, Feb 25||FPGA Architectures, Cont.|
|M, Feb 28||FPGA Architectures, Cont.|
|W, March 2||Class cancelled|
|F, March 4||2-process FSM+D||Examples used in class|
|M, March 14||Midterm 2 Review|
|W, March 16||No class|
|F, March 18||Midterm 2|
|M, March 21||Tristate buffers, Bidirectional buses||Code|
|W, March 23||Small8 Intro, Deliverables 1+2|
|F, March 25||Small8 Deliverable 3|
|M, March 28||Small8 Instruction set|
|W, March 30||Small8 Instruction set|
|F, April 1||Metastability, clock domain crossing||Related papers|
|M, April 4||Metastability, cont.|
|W, April 6||Metastability, cont.
|F, April 8||Parallelism, cont.
|M, April 11||Parallelism, cont.
|W, April 13||Special Topics: Intermediate Fabrics