EEL4712 Digital Design (Spring 2010)


There will be no final. Instead, we will have a 3rd midterm on the last day of classes (Wed April 21).

Previous Midterms

Catalog Description

Advanced modular logic, design languages, finite state machines and binary logic.


This course will review basic concepts in digital logic (muxes, decoders, encoders, etc.) and will build upon these concepts to form complex digital circuits consisting of finite state machines, controllers, and datapaths. The course will be lab intensive and will provide realistic case studies to apply concepts learned during lecture. All concepts discussed in lecture will be implemented in VHDL.

Course Information


Date Topic Slides/Reading Material
W, January 6 Course info, Intro Intro
F, January 8 VHDL Intro No slides, read ch.6 (combinational-circuit building blocks), read over lab 0 documentation.
M, January 11 No class
W, January 13 Behavioral Combinational Logic
F, January 15 Lab 1 discussion, Structural Architectures Read lab 1 instructions
W, January 20 Arithmetic Operations in std_logic_arith and numeric_std Add w/ carry examples in different packages:
std_logic_arith with std_logic_unsigned

Common Problems:
Signal/variable comparison
F, January 22 Test benches Do ModelSim tutorial for lab2
M, January 25 Inferred Latches, Generics, Generate Statements
W, January 27 Case study: Carry-lookahead adder Read section 5.4
Read lab 3 description
F, January 29 Sequential Logic, Finite State Machines ADDED: Read Ch. 7.12 to end of Ch.7 for VHDL examples.
M, Feb 1 Finite State Machines 1-process FSM
2-process FSM
W, Feb 3 Finite State Machines with Integrated Datapaths (FSMD) Fibonacci Calculator FSMD (1-process model)
Make sure to compare this with the FSM+D model posted later.
F, Feb 5 Lab 4 Read lab instructions.
M, Feb 8 Finite State Machines + Explicit Datapaths (FSM+D) Fibonacci Calculator FSM+D
fib, datapath, and ctrl are the most important entities. Make sure to compare this with the FSMD model posted earlier.
W, Feb 10 Midterm 1 Review
F, Feb 12 Midterm 1
M, Feb 15 Midterm 1 Discussion
Misc. VHDL (integers, arrays, packages)
W, Feb 17 Lab 5 (GCD Calculator)
Misc. VHDL (integers, arrays, packages, functions)
F, Feb 19 Memories Altera Guidelines for Memories (pg.12-35)
Xilinx Guidelines for Memories (pg.144-195)
M, Feb 22 No class
W, Feb 24 VGA Interfacing Read Lab 6
F, Feb 26 FPGA Architectures FPGA Architecture Slides
Cyclone II Datasheet
Cyclone II Figures
Cyclone II Family Overview
M, March 1 FPGA Architectures, Cont.
W, March 3 FPGA Architectures, Cont.
F, March 5 2-process FSM+D Examples used in class
M, March 15 VHDL Arrays
W, March 17 Class Cancelled
F, March 19 Midterm 2 Review
M, March 22 Small8 Lab Intro, Tri-State Buffers, Buses
March 24-April Small8, Cont.
F, March 26 Midterm 2
M, March 29 Midterm 2 Discussion
W, March 31 Small8 Lab Intro, Tri-State Buffers, Buses
F, April 2 Small8, Cont.
W, April 7 Small8, Cont.
F, April 9 Small8, Cont.
M, April 12 Parallelism Slides
W, April 14 Parallelism, Cont.
F, April 16 Parallelism, Review

VHDL Resources