Lab 2 - Nallatech Tutorial


Announcement - You will be working in groups of 4 on this project.

Turn in the project using the e-learning website (there is a link of the main course page). Please zip all source files from part 2 (DimeTalk project, C files, etc.) and attach it to your submission. Please do not turn in files that are generated during synthesis. You only need one submission per group. Include a readme.txt files that lists all group members in addition to any other information that might be needed by the grader.

Introduction

In this lab, you will be learning the basics of the Nallatech board and the DIMETalk design environment.

Part 1 - Installation/Tutorial

  1. Follow the Dimetalk installation instructions that you will receive by email.
  2. After installing the tools, perform this tutorial to become familiar with the environment
  3. You will also need these files, which are referenced in the tutorial. You can untar and unzip the file with this command: tar xzvf tutorial.tgz.

Once you are done I highly recommend reading the following. Although not required for this assignment, you will be using these documents on all following projects. If you are uncertain about the functionality of anything in DIMETalk, make sure to find the answer in here, or ask me.

  1. DIMETalk User Guide
  2. DIMETalk Reference Guide

Part 2 - Simple application

In the second part of the lab, you will use what you learned in part 1 to develop a simple application that uses block RAMS inside the FPGA on the Nallatech board. No VHDL is required for this tutorial.

The architecture will be the same as in the previous tutorial, although if you like, you may modify the size of the blockRAMs (by changing the width of the address lines) to reduce the size of your design.

Once you have created the architecture in DIMETalk, you will write a modified C program that initializes BRAM1 with 10 integers (1 through 10) and initializes BRAM2 with 10 integers (11 through 20). Your code will then update BRAM3 one element at at time with the product of values from BRAM1 and BRAM2. In other words: 

for (i=0; i < 10; i++)
  BRAM3[i] = BRAM1[i] * BRAM2[i];

This is not the syntax you would use, but this is the behavior that should be achieved. Note that you must read/write each individual array element from the block RAMs as opposed to simply using a temporary array in the C code (in which case no communication with the board would be performed). For this lab, the multiplication is not done on the FPGA, you are simply using the memories on the FPGA to store the arrays. The pseudocode for the loop looks like the following: 

for (i=0; i < 10; i++ {
  read 1 32-bit word from address i of BRAM1;
  read 1 32-bit word from address i of BRAM2;
  multiply the 2 words;
  write the product (1 32-bit word) to address i of BRAM3;
}

After the loop has finished, read the contents of BRAM3 into an array and then print the results to the screen to verify that everything worked.