The first midterm will be given on Monday, October 13th. It will cover
everything up to systolic arrays. The test will be mostly multiple choice
with a few open answer questions.
Fundamental concepts at advanced undergraduate level (EEL4930) and introductory graduate level (EEL5934) in reconfigurable computing based upon advanced technologies in field-programmable logic devices. Topics include general concepts, device architectures, design tools, metrics and kernels, system architectures, and application case studies.
| Date | Topic | Slides/Reading Material |
|---|---|---|
| M, August 25 | Course info, Intro to RC |
Slides Paper - Compton, Hauck Survey |
| W, August 27 | Intro to RC |
Slides |
| F, August 29 | VHDL Tutorial (Basics) | |
| W, September 3 | VHDL Tutorial (Behavioral Descriptions) | |
| F, September 5 | VHDL Tutorial (Structural Descriptions, FSMs) | |
| M, September 8 | RC Architectures | Slides |
| W, September 10 | RC Architectures | Slides |
| F, September 12 | RC Architectures | Slides |
| M, September 15 | RC Architectures | Updated Slides (version 1.6) |
| W, September 17 | Nallatech | Nallatech Slides |
| F, September 19 | NP-Completeness, Optimization Problems, Heuristics | Slides |
| M, September 22 | RT Synthesis, Placement |
Slides
Paper - Placement/Routing |
| W, September 24 | Routing |
Slides
Maze Router Demo Versatile Place and Route (VPR) illustrations |
| M, September 29 | Systolic Arrays | Slides |
| W, October 1 | Systolic Arrays, Cont. | |
| F, October 3 | Systolic Arrays, Cont. | |
| M, October 6 | Systolic Arrays, Cont. | Paper - A Quantitative Analysis of the Speedup Factors of FPGAs over Processors |
| W, October 8 | Lab 4 Discussion | |
| F, October 10 | Midterm Review | |
| M, October 13 | Midterm 1 | |
| W, October 15 | Final Project Discussion | |
| F, October 17 | High-level Synthesis | Slides |
| M-F, October 20-24 | No Lectures | |
| M, October 27 | High-level Synthesis, Cont. | |
| W, October 29 | High-level Synthesis, Cont. | |
| F, October 31 | High-level Synthesis, Cont. | |
| M, November 3 | High-level Synthesis, Cont. | |
| W, November 5 | Buffering Techniques |
Slides
Smart Buffer Paper |
| F, November 7 | Buffering Techniques | |
| M, November 10 | Hw/Sw Partitioning |
Hw/Sw Partitioning Slides
System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search An Evaluation of Bipartitioning Techniques |
| W, November 12 | Hw/Sw Partitioning | |
| F, November 14 | Hw/Sw Partitioning | |
| M, November 17 | Warp Processors |
Warp Processing Slides
Warp Processors Thread Warping |
| W, Nov 19 | Performance Analysis |
Slides
Paper |
| F, Nov 21 | Formulation, RCML |
Slides
No paper |
| M, Nov 24 | Device Characterization |
Slides
Paper |
| W, Nov 26 | SCL, Target Tracking |
Target Tracking Slides
SCL Slides |