-- Greg Stitt
-- University of Florida

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity GLUE_LOGIC is
  port(
    clk    : in  std_logic;
    rst    : in  std_logic;
    addr   : in  std_logic_vector(31 downto 0);
    en     : in  std_logic;
    wen    : in  std_logic;
    din    : in  std_logic_vector(31 downto 0);
    dout   : out std_logic_vector(31 downto 0);
    go     : out std_logic;
    n      : out std_logic_vector(31 downto 0);
    result : in  std_logic_vector(31 downto 0);
    done   : in  std_logic
    );

  attribute dtinfo         : string;
  attribute dtinfo of clk  : signal  is "clk1";
  attribute dtinfo of rst  : signal  is "reset";
  attribute dtinfo of addr : signal is "usergroup, MMAP";
  attribute dtinfo of go   : signal   is "usergroup, IO";

end GLUE_LOGIC;

architecture bhv of GLUE_LOGIC is

  signal reg_go : std_logic;
  signal reg_n  : std_logic_vector(31 downto 0);

begin

  process(clk, rst) is
  begin

    if (rst = '1') then
      reg_go <= '0';
      reg_n  <= std_logic_vector(to_unsigned(10, 32));
      dout   <= std_logic_vector(to_unsigned(10, 32));

    elsif (clk'event and clk = '1') then

      -- if a write
      if (en = '1' and wen = '1') then

        case addr(1 downto 0) is
          when "00" =>
            reg_go <= din(0);
          when "01" =>
            reg_n  <= din;

            -- result and done are read only
          when others => null;
        end case;

        -- if a read
      elsif (en = '1' and wen = '0') then

        case addr(1 downto 0) is
          when "00" =>
            dout <= std_logic_vector(to_unsigned(0, 31)) & reg_go;
          when "01" =>
            dout <= reg_n;
          when "10" =>
            dout <= result;
          when "11" =>
            dout <= std_logic_vector(to_unsigned(0, 31)) & done;

          when others => null;
        end case;
      end if;

    end if;
  end process;

  go <= reg_go;
  n  <= reg_n;

end bhv;