EEL4712 Digital Design (Spring 2017)


My Tuesday office hours have now moved to period 3.

Previous Midterms

Midterm 1 will be on Friday, Feb 10 in class. Midterm 2 will be on Friday, March 17. Midterm 3 will be Wed, April 19. There is no final.

Catalog Description

Advanced modular logic, design languages, finite state machines and binary logic.


This course will review basic concepts in digital logic (muxes, decoders, encoders, etc.) and will build upon these concepts to form complex digital circuits consisting of finite state machines, controllers, and datapaths. The course will be lab intensive and will provide realistic case studies to apply concepts learned during lecture. All concepts discussed in lecture will be implemented in VHDL.

Course Information


Date Topic Slides/Reading Material
W, January 4 Course Intro Slides
F, January 6 VHDL Intro (guidelines, entity and architecture, basic mux implementation) Tutorial
M, January 9 VHDL Intro (if vs. case, priority encoder, structural architectures) Tutorial (read combinational logic and structural description sections)
4x1 mux
See Ch. 6 for priority encoder example.
W, January 11 Lab 1
Structural Architectures, Cont.
F, January 13 Arithmetic Operations Add w/ carry examples in different packages:
std_logic_arith with std_logic_unsigned

Common Problems:
Signal/variable comparison
M, January 16 Holiday
W, January 18 Lab 2, Generics, Avoiding Latches, Testbenches
F, January 20 Testbenches, Cont.
Carry-Lookahead Adders
Read Section 5.4
M, January 23 Lab 3, For-generate
W, January 25 Misc. VHDL (initialization of signals, advanced testbenches, generics, components, vho/vhd, package reference)
F, January 27 Sequential Logic (see tutorial examples)
M, January 30 Synthesis of Sequential Logic (see tutorial examples)
M, Feb 1 Finite State Machines See tutorial. Direct link.
F, Feb 3 Midterm 1 Review
M, Feb 6 Lab 4 See counter example in sequential logic section of the tutorial.
W, Feb 8 No Class
F, Feb 10 Midterm 1
M, Feb 13 FSMD See Controllers+Datapath section of VHDL tutorial.
Fibonacci Calculator FSMD (1-process model)
Fibonacci code and datapath
W, Feb 15 FSM+D Code to be shared later.
F, Feb 17 FSM+D, Cont. Code to be shared later.
M, Feb 20 Lab 6
W, Feb 22 Lab 6
F, Feb 24 Arrays, If Generate See delay example on tutorial.
M, Feb 27 FPGA Architectures FPGA Architecture Slides
Cyclone II Datasheet
Cyclone II Figures
Cyclone II Family Overview
Cyclone III Family Handbook
Cyclone III Family Overview
W, March 1 FPGA Architectures, Cont.
F, March 3 Class Cancelled
M, March 13 Midterm 2 Review
W, March 15 MIPS Project (Register File, RAM) RAM Code
F, March 17 Midterm 2
M, March 20 MIPS Project (Register File)
W, March 22 MIPS Project (ALU, datapath)
F, March 24 Testbench Recommendations, Buses, Tristates Bus/Tristate Code
M, March 27 MIPS Datapath, Memory, Ports, RAM, R-type instructions
W, March 29 MIPS I-type instructions
F, March 31 MIPS branch/jump instructions
M, April 3 MIPS jump instructions, MIF Files
W, April 5 Class Cancelled
F, April 7 Research Overview Virtualization Slides
M, April 10 Metastability, Clock-Domain Crossing Papers
W, April 12 Pareto Optimality
Design-space exploration
F, April 14 Design-space exploration, cont.
Sliding-Window Paper
Sliding-Window Slides
M, April 17 Midterm 3 Review

VHDL Resources